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Lokesh Vutlaaaa449f2018-08-27 15:57:54 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Texas Instruments' K3 SD Host Controller Interface
6 */
7
8#include <clk.h>
9#include <common.h>
10#include <dm.h>
11#include <malloc.h>
12#include <power-domain.h>
Faiz Abbasce142ff2019-06-11 00:43:38 +053013#include <regmap.h>
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +053014#include <sdhci.h>
15
Faiz Abbasce142ff2019-06-11 00:43:38 +053016/* CTL_CFG Registers */
17#define CTL_CFG_2 0x14
18
19#define SLOTTYPE_MASK GENMASK(31, 30)
20#define SLOTTYPE_EMBEDDED BIT(30)
21
22/* PHY Registers */
23#define PHY_CTRL1 0x100
24#define PHY_CTRL2 0x104
25#define PHY_CTRL3 0x108
26#define PHY_CTRL4 0x10C
27#define PHY_CTRL5 0x110
28#define PHY_CTRL6 0x114
29#define PHY_STAT1 0x130
30#define PHY_STAT2 0x134
31
32#define IOMUX_ENABLE_SHIFT 31
33#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
34#define OTAPDLYENA_SHIFT 20
35#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
36#define OTAPDLYSEL_SHIFT 12
37#define OTAPDLYSEL_MASK GENMASK(15, 12)
38#define STRBSEL_SHIFT 24
39#define STRBSEL_MASK GENMASK(27, 24)
40#define SEL50_SHIFT 8
41#define SEL50_MASK BIT(SEL50_SHIFT)
42#define SEL100_SHIFT 9
43#define SEL100_MASK BIT(SEL100_SHIFT)
44#define DLL_TRIM_ICP_SHIFT 4
45#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
46#define DR_TY_SHIFT 20
47#define DR_TY_MASK GENMASK(22, 20)
48#define ENDLL_SHIFT 1
49#define ENDLL_MASK BIT(ENDLL_SHIFT)
50#define DLLRDY_SHIFT 0
51#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
52#define PDB_SHIFT 0
53#define PDB_MASK BIT(PDB_SHIFT)
54#define CALDONE_SHIFT 1
55#define CALDONE_MASK BIT(CALDONE_SHIFT)
56#define RETRIM_SHIFT 17
57#define RETRIM_MASK BIT(RETRIM_SHIFT)
58
59#define DRIVER_STRENGTH_50_OHM 0x0
60#define DRIVER_STRENGTH_33_OHM 0x1
61#define DRIVER_STRENGTH_66_OHM 0x2
62#define DRIVER_STRENGTH_100_OHM 0x3
63#define DRIVER_STRENGTH_40_OHM 0x4
64
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053065#define AM654_SDHCI_MIN_FREQ 400000
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +053066
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053067struct am654_sdhci_plat {
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +053068 struct mmc_config cfg;
69 struct mmc mmc;
Faiz Abbasce142ff2019-06-11 00:43:38 +053070 struct regmap *base;
71 bool non_removable;
72 u32 otap_del_sel;
73 u32 trm_icp;
74 u32 drv_strength;
Faiz Abbas794453f2019-06-13 10:29:51 +053075 u32 flags;
76#define DLL_PRESENT (1 << 0)
Faiz Abbasce142ff2019-06-11 00:43:38 +053077 bool dll_on;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +053078};
79
Faiz Abbasf6058072019-06-11 00:43:41 +053080static void am654_sdhci_set_control_reg(struct sdhci_host *host)
81{
82 struct mmc *mmc = (struct mmc *)host->mmc;
83 u32 reg;
84
85 if (IS_SD(host->mmc) &&
86 mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
87 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
88 reg |= SDHCI_CTRL_VDD_180;
89 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
90 }
91
92 sdhci_set_uhs_timing(host);
93}
94
Faiz Abbasce142ff2019-06-11 00:43:38 +053095static int am654_sdhci_set_ios_post(struct sdhci_host *host)
96{
97 struct udevice *dev = host->mmc->dev;
98 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
99 unsigned int speed = host->mmc->clock;
100 int sel50, sel100;
101 u32 mask, val;
102 int ret;
103
104 /* Reset SD Clock Enable */
105 val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
106 val &= ~SDHCI_CLOCK_CARD_EN;
107 sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
108
109 /* power off phy */
110 if (plat->dll_on) {
111 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
112
113 plat->dll_on = false;
114 }
115
116 /* restart clock */
117 sdhci_set_clock(host->mmc, speed);
118
119 /* switch phy back on */
120 if (speed > AM654_SDHCI_MIN_FREQ) {
121 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
122 val = (1 << OTAPDLYENA_SHIFT) |
123 (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
124 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
125 switch (speed) {
126 case 200000000:
127 sel50 = 0;
128 sel100 = 0;
129 break;
130 case 100000000:
131 sel50 = 0;
132 sel100 = 1;
133 break;
134 default:
135 sel50 = 1;
136 sel100 = 0;
137 }
138
139 /* Configure PHY DLL frequency */
140 mask = SEL50_MASK | SEL100_MASK;
141 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
142 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
143
144 /* Enable DLL */
145 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
146 0x1 << ENDLL_SHIFT);
147 /*
148 * Poll for DLL ready. Use a one second timeout.
149 * Works in all experiments done so far
150 */
151 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
152 val & DLLRDY_MASK, 1000, 1000000);
153 if (ret)
154 return ret;
155
156 plat->dll_on = true;
157 }
158
159 return 0;
160}
161
162const struct sdhci_ops am654_sdhci_ops = {
Faiz Abbasf6058072019-06-11 00:43:41 +0530163 .set_ios_post = &am654_sdhci_set_ios_post,
164 .set_control_reg = &am654_sdhci_set_control_reg,
Faiz Abbasce142ff2019-06-11 00:43:38 +0530165};
166
Faiz Abbas794453f2019-06-13 10:29:51 +0530167const struct sdhci_ops j721e_4bit_sdhci_ops = {
168 .set_control_reg = &am654_sdhci_set_control_reg,
169};
170
Faiz Abbasce142ff2019-06-11 00:43:38 +0530171int am654_sdhci_init(struct am654_sdhci_plat *plat)
172{
173 u32 ctl_cfg_2 = 0;
174 u32 mask, val;
175 int ret;
176
177 /* Reset OTAP to default value */
178 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
179 regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
180
Faiz Abbas794453f2019-06-13 10:29:51 +0530181 if (plat->flags & DLL_PRESENT) {
182 regmap_read(plat->base, PHY_STAT1, &val);
183 if (~val & CALDONE_MASK) {
184 /* Calibrate IO lines */
185 regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
186 PDB_MASK);
187 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
188 val, val & CALDONE_MASK,
189 1, 20);
190 if (ret)
191 return ret;
192 }
193
194 /* Configure DLL TRIM */
195 mask = DLL_TRIM_ICP_MASK;
196 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
197
198 /* Configure DLL driver strength */
199 mask |= DR_TY_MASK;
200 val |= plat->drv_strength << DR_TY_SHIFT;
201 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
Faiz Abbasce142ff2019-06-11 00:43:38 +0530202 }
203
Faiz Abbasce142ff2019-06-11 00:43:38 +0530204 /* Enable pins by setting IO mux to 0 */
205 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
206
207 /* Set slot type based on SD or eMMC */
208 if (plat->non_removable)
209 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
210
211 regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
212
213 return 0;
214}
215
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530216static int am654_sdhci_probe(struct udevice *dev)
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530217{
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530218 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530219 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
220 struct sdhci_host *host = dev_get_priv(dev);
Faiz Abbasce142ff2019-06-11 00:43:38 +0530221 struct mmc_config *cfg = &plat->cfg;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530222 struct clk clk;
223 unsigned long clock;
224 int ret;
225
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530226 ret = clk_get_by_index(dev, 0, &clk);
227 if (ret) {
228 dev_err(dev, "failed to get clock\n");
229 return ret;
230 }
231
232 clock = clk_get_rate(&clk);
233 if (IS_ERR_VALUE(clock)) {
234 dev_err(dev, "failed to get rate\n");
235 return clock;
236 }
237
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530238 host->max_clk = clock;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530239 host->mmc = &plat->mmc;
Faiz Abbasce142ff2019-06-11 00:43:38 +0530240 host->mmc->dev = dev;
241 ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
242 AM654_SDHCI_MIN_FREQ);
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530243 if (ret)
244 return ret;
Faiz Abbas794453f2019-06-13 10:29:51 +0530245 host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530246 host->mmc->priv = host;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530247 upriv->mmc = host->mmc;
248
Faiz Abbasce142ff2019-06-11 00:43:38 +0530249 regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
250
251 am654_sdhci_init(plat);
252
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530253 return sdhci_probe(dev);
254}
255
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530256static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530257{
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530258 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530259 struct sdhci_host *host = dev_get_priv(dev);
Faiz Abbasce142ff2019-06-11 00:43:38 +0530260 struct mmc_config *cfg = &plat->cfg;
261 u32 drv_strength;
262 int ret;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530263
264 host->name = dev->name;
265 host->ioaddr = (void *)dev_read_addr(dev);
Faiz Abbasce142ff2019-06-11 00:43:38 +0530266 plat->non_removable = dev_read_bool(dev, "non-removable");
267
Faiz Abbas794453f2019-06-13 10:29:51 +0530268 if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
269 device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
270 plat->flags |= DLL_PRESENT;
Faiz Abbasce142ff2019-06-11 00:43:38 +0530271
272 ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
273 if (ret)
274 return ret;
275
Faiz Abbas794453f2019-06-13 10:29:51 +0530276 if (plat->flags & DLL_PRESENT) {
277 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
278 if (ret)
279 return ret;
Faiz Abbasce142ff2019-06-11 00:43:38 +0530280
Faiz Abbas794453f2019-06-13 10:29:51 +0530281 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
282 &drv_strength);
283 if (ret)
284 return ret;
285
286 switch (drv_strength) {
287 case 50:
288 plat->drv_strength = DRIVER_STRENGTH_50_OHM;
289 break;
290 case 33:
291 plat->drv_strength = DRIVER_STRENGTH_33_OHM;
292 break;
293 case 66:
294 plat->drv_strength = DRIVER_STRENGTH_66_OHM;
295 break;
296 case 100:
297 plat->drv_strength = DRIVER_STRENGTH_100_OHM;
298 break;
299 case 40:
300 plat->drv_strength = DRIVER_STRENGTH_40_OHM;
301 break;
302 default:
303 dev_err(dev, "Invalid driver strength\n");
304 return -EINVAL;
305 }
Faiz Abbasce142ff2019-06-11 00:43:38 +0530306 }
307
308 ret = mmc_of_parse(dev, cfg);
309 if (ret)
310 return ret;
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530311
312 return 0;
313}
314
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530315static int am654_sdhci_bind(struct udevice *dev)
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530316{
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530317 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530318
319 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
320}
321
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530322static const struct udevice_id am654_sdhci_ids[] = {
Faiz Abbas794453f2019-06-13 10:29:51 +0530323 {
324 .compatible = "ti,am654-sdhci-5.1",
325 .data = (ulong)&am654_sdhci_ops,
326 },
327 {
328 .compatible = "ti,j721e-sdhci-8bit",
329 .data = (ulong)&am654_sdhci_ops,
330 },
331 {
332 .compatible = "ti,j721e-sdhci-4bit",
333 .data = (ulong)&j721e_4bit_sdhci_ops,
334 },
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530335 { }
336};
337
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530338U_BOOT_DRIVER(am654_sdhci_drv) = {
339 .name = "am654_sdhci",
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530340 .id = UCLASS_MMC,
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530341 .of_match = am654_sdhci_ids,
342 .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530343 .ops = &sdhci_ops,
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530344 .bind = am654_sdhci_bind,
345 .probe = am654_sdhci_probe,
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530346 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530347 .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
Lokesh Vutlaaaa449f2018-08-27 15:57:54 +0530348};