| Wang Huan | c8a7d9d | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_TARGET_LS1021ATWR=y | ||||
| Bin Meng | 8b67761 | 2016-01-13 19:39:05 -0800 | [diff] [blame] | 3 | CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" |
| Tom Rini | 877a1a3 | 2017-08-11 11:20:19 -0400 | [diff] [blame] | 4 | CONFIG_DISTRO_DEFAULTS=y |
| Alison Wang | 397b0d9 | 2016-05-04 12:45:55 +0800 | [diff] [blame] | 5 | CONFIG_FIT=y |
| 6 | CONFIG_FIT_VERBOSE=y | ||||
| Heiko Schocher | bb597c0 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 7 | CONFIG_OF_BOARD_SETUP=y |
| 8 | CONFIG_OF_STDOUT_VIA_ALIAS=y | ||||
| 9 | CONFIG_BOOTDELAY=3 | ||||
| Sam Protsenko | 5abc1a4 | 2017-08-14 20:22:17 +0300 | [diff] [blame] | 10 | CONFIG_USE_BOOTARGS=y |
| 11 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" | ||||
| Simon Glass | 98af879 | 2016-10-17 20:12:35 -0600 | [diff] [blame] | 12 | CONFIG_SILENT_CONSOLE=y |
| Simon Glass | ef26d60 | 2016-10-17 20:12:37 -0600 | [diff] [blame] | 13 | # CONFIG_CONSOLE_MUX is not set |
| 14 | CONFIG_SYS_CONSOLE_IS_IN_ENV=y | ||||
| Tuomas Tynkkynen | ad12dc1 | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 15 | CONFIG_CMD_IMLS=y |
| Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 16 | CONFIG_CMD_GREPENV=y |
| Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 17 | CONFIG_CMD_MEMINFO=y |
| Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 18 | CONFIG_CMD_MEMTEST=y |
| Patrick Delaunay | b331cd6 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 19 | CONFIG_CMD_GPT=y |
| Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 20 | CONFIG_CMD_I2C=y |
| Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 21 | CONFIG_CMD_MMC=y |
| Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 22 | CONFIG_CMD_USB=y |
| Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 23 | # CONFIG_CMD_SETEXPR is not set |
| Simon Glass | 0f71025 | 2017-04-26 22:27:55 -0600 | [diff] [blame] | 24 | CONFIG_CMD_BMP=y |
| Bin Meng | f833cd6 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 25 | CONFIG_OF_CONTROL=y |
| Tom Rini | 5dc4dfd | 2017-08-28 07:16:32 -0400 | [diff] [blame] | 26 | CONFIG_ENV_IS_IN_FLASH=y |
| Bin Meng | f833cd6 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 27 | CONFIG_DM=y |
| Tom Rini | 2852267 | 2017-03-01 16:51:58 -0500 | [diff] [blame] | 28 | CONFIG_FSL_CAAM=y |
| Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 29 | CONFIG_MTD_NOR_FLASH=y |
| Alexandru Gagniuc | 3146f0c | 2017-08-01 17:19:59 -0700 | [diff] [blame] | 30 | CONFIG_PHYLIB=y |
| Simon Glass | a77fda1 | 2015-08-19 09:33:43 -0600 | [diff] [blame] | 31 | CONFIG_NETDEVICES=y |
| Tom Rini | 1989374 | 2017-08-07 22:00:34 -0400 | [diff] [blame] | 32 | CONFIG_PHY_GIGE=y |
| Simon Glass | a77fda1 | 2015-08-19 09:33:43 -0600 | [diff] [blame] | 33 | CONFIG_E1000=y |
| Patrick Delaunay | b331cd6 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 34 | CONFIG_PCI=y |
| 35 | CONFIG_DM_PCI=y | ||||
| 36 | CONFIG_DM_PCI_COMPAT=y | ||||
| 37 | CONFIG_PCIE_LAYERSCAPE=y | ||||
| Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 38 | CONFIG_DM_SERIAL=y |
| Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 39 | CONFIG_SYS_NS16550=y |
| Masahiro Yamada | 0a8cc1a | 2016-06-04 07:35:03 +0900 | [diff] [blame] | 40 | CONFIG_USB=y |
| Alison Wang | 563ac65 | 2017-07-07 15:10:17 +0800 | [diff] [blame] | 41 | CONFIG_DM_USB=y |
| Masahiro Yamada | 0a8cc1a | 2016-06-04 07:35:03 +0900 | [diff] [blame] | 42 | CONFIG_USB_XHCI_HCD=y |
| Masahiro Yamada | 10db750 | 2016-06-04 07:35:04 +0900 | [diff] [blame] | 43 | CONFIG_USB_XHCI_DWC3=y |
| Tom Rini | 645176d | 2016-09-08 16:31:26 -0400 | [diff] [blame] | 44 | CONFIG_USB_STORAGE=y |
| Sanchayan Maity | b215fb3 | 2017-04-11 11:12:09 +0530 | [diff] [blame] | 45 | CONFIG_VIDEO_FSL_DCU_FB=y |
| Tom Rini | 73dd818 | 2017-10-30 12:58:33 -0400 | [diff] [blame^] | 46 | CONFIG_VIDEO=y |
| Tom Rini | 2681e78 | 2017-05-01 11:41:11 -0400 | [diff] [blame] | 47 | # CONFIG_VIDEO_SW_CURSOR is not set |