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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MOUSSE/MPC8240 Board definitions.
3 * For more info, see http://www.vooha.com/
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * (C) Copyright 2001
9 * James Dougherty (jfd@cs.stanford.edu)
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __MOUSSE_H
31#define __MOUSSE_H
32
33/* System addresses */
34
35#define PCI_SPECIAL_BASE 0xfe000000
36#define PCI_SPECIAL_SIZE 0x01000000
37
38/* PORTX Device Addresses for Mousse */
39
40#define PORTX_DEV_BASE 0xff000000
41#define PORTX_DEV_SIZE 0x01000000
42
43#define ENET_DEV_BASE 0x80000000
44
45#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000)
46#define PLD_REG(off) (*(volatile unsigned char *) \
47 (PLD_REG_BASE + (off)))
48
49#define PLD_REVID_B1 0x7f
50#define PLD_REVID_B2 0x01
51
52/* MPLD */
53#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
54#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
55#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
56#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
57#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
58#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
59#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
60#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
61
62/* SGS M48T59Y */
63#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000)
64#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
65#define TOD_NVRAM_BASE TOD_BASE
66#define TOD_NVRAM_SIZE 0x1ff0
67#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
68
69/* NS16552 SIO */
70#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
71#define N_SIO_CHANNELS 2
72#define N_COM_PORTS N_SIO_CHANNELS
73
74/*
75 * On-board Dec21143 PCI Ethernet
76 * Note: The PCI MBAR chosen here was used from MPC8240UM which states
77 * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
78 * is set, then PCI memory maps 1-1 with this address range in the
79 * correct byte order.
80 */
81#define PCI_ENET_IOADDR 0x80000000
82#define PCI_ENET_MEMADDR 0x80000000
83
84/*
85 * Flash Memory Layout
86 *
87 * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB
88 * sector SA3 is obscured by the 32 kB serial/TOD access space, and
89 * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
90 * containing the fixed boot ROM. (If the 512 kB PLCC is
91 * deconfigured by jumper, this window to Flash Bank 0 becomes
92 * visible, but it still contains the fixed boot code and should be
93 * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8
94 * kB), and SA2 (8 kB) are currently unused.
95 *
96 * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully
97 * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore
98 * 16-bit words only exist at addresses that are multiples of 8. All
99 * PROM data and control addresses must be multiplied by 8.
100 *
101 * See flashMap.c for description of flash filesystem layout.
102 */
103
104/*
105 * FLASH memory address space: 8-bit wide FLASH memory spaces.
106 */
107#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */
108#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */
109#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */
110
111#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */
112#define FLASH0_SEG1_END 0xffefffff /* 960 kB */
113#define FLASH0_SEG1_SIZE 0x000f0000
114
115#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */
116#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */
117#define FLASH0_SEG2_SIZE 0x00080000
118
119#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */
120#define FLASH0_SEG3_END 0xffffffff
121#define FLASH0_SEG3_SIZE 0x00080000
122
123/* Where Kahlua starts */
124#define FLASH_RESET_VECT 0xfff00100
125
126/*
127 * CHRP / PREP (MAP A/B) definitions.
128 */
129
130#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
131#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
132/* MPC107 (MPC8240 internal EUMBBAR mapped) */
133#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */
134#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */
135
136/*
137 * Mousse PCI IDSEL Assignments (Device Number)
138 */
139#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */
140#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */
141#define MOUSSE_IDSEL_82371 15 /* That other thing */
142#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */
143#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */
144#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */
145#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */
146#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */
147
148/*
149 * Mousse Interrupt Mapping:
150 *
151 * IRQ1 Enet (intA|intB|intC|intD)
152 * IRQ2 CPCI intA (See below)
153 * IRQ3 Local PCI slot intA|intB|intC|intD
154 * IRQ4 COM1 Serial port (Actually higher addressed port on duart)
155 *
156 * PCI Interrupt Mapping in CPCI chassis:
157 *
158 * | CPCI Slot
159 * | 1 (CPU) 2 3 4 5 6
160 * -----------+--------+-------+-------+-------+-------+-------+
161 * intA | X X X
162 * intB | X X X
163 * intC | X X X
164 * intD | X X X
165 */
166
167
168#define EPIC_VECTOR_EXT0 0
169#define EPIC_VECTOR_EXT1 1
170#define EPIC_VECTOR_EXT2 2
171#define EPIC_VECTOR_EXT3 3
172#define EPIC_VECTOR_EXT4 4
173#define EPIC_VECTOR_TM0 16
174#define EPIC_VECTOR_TM1 17
175#define EPIC_VECTOR_TM2 18
176#define EPIC_VECTOR_TM3 19
177#define EPIC_VECTOR_I2C 20
178#define EPIC_VECTOR_DMA0 21
179#define EPIC_VECTOR_DMA1 22
180#define EPIC_VECTOR_I2O 23
181
182
183#define INT_VEC_IRQ0 0
184#define INT_NUM_IRQ0 INT_VEC_IRQ0
185#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */
186#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */
187#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */
188#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */
189
190/* Onboard DEC 21143 Ethernet */
191#define PCI_ENET_MEMADDR 0x80000000
192#define PCI_ENET_IOADDR 0x80000000
193
194/* Some other PCI device */
195#define PCI_SLOT_MEMADDR 0x81000000
196#define PCI_SLOT_IOADDR 0x81000000
197
198/* Promise ATA66 PCI Device (ATA controller) */
199#define PROMISE_MBAR0 0xa0000000
200#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000)
201#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000)
202#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000)
203#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000)
204#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000)
205
206/* ATA/66 Controller offsets */
207#define CFG_ATA_BASE_ADDR PROMISE_MBAR0
208#define CFG_IDE_MAXBUS 2 /* ide0/ide1 */
209#define CFG_IDE_MAXDEVICE 2 /* 2 drives per controller */
210#define CFG_ATA_IDE0_OFFSET 0
211#define CFG_ATA_IDE1_OFFSET 0x3000
212/*
213 * Definitions for accessing IDE controller registers
214 */
215#define CFG_ATA_DATA_OFFSET 0
216#define CFG_ATA_REG_OFFSET 0
217#define CFG_ATA_ALT_OFFSET (0x1000)
218
219/*
220 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
221 * are defined in config.h and Makefile.
222 * All definitions for these constants must be identical.
223 */
224#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */
225#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */
226#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
227#define ROM_SIZE 0x00080000 /* 512KB ROM space */
228#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */
229#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */
230
231/*
232 * NVRAM configuration
233 * NVRAM is implemented via the SGS Thomson M48T59Y
234 * 64Kbit (8Kbx8) Timekeeper SRAM.
235 * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information.
236 */
237
238#define NV_RAM_ADRS TOD_NVRAM_BASE
239#define NV_RAM_INTRVL 1
240#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT()
241#define NV_RAM_WR_DSBL SYS_TOD_PROTECT()
242
243#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */
244#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */
245#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/
246#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */
247#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */
248#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */
249#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */
250#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */
251#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */
252#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */
253#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */
254#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/
255#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */
256#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1)
257#define NV_RAM_SIZE 8176 /* NVRAM End */
258
259#endif /* __MOUSSE_H */