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trembcc05c72013-09-10 22:08:39 +02001/*
2 * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
8#include <generated/asm-offsets.h>
9#include <version.h>
10#include <asm/macro.h>
11#include <asm/arch/imx-regs.h>
12#include "apf27.h"
13
14 .macro init_aipi
15 /*
16 * setup AIPI1 and AIPI2
17 */
18 write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
19 write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
20 write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
21 write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
22
23 /* Change SDRAM signal strengh */
24 ldr r0, =GPCR
25 ldr r1, =ACFG_GPCR_VAL
26 ldr r5, [r0]
27 orr r5, r5, r1
28 str r5, [r0]
29
30 .endm /* init_aipi */
31
32 .macro init_clock
33 ldr r0, =CSCR
34 /* disable MPLL/SPLL first */
35 ldr r1, [r0]
36 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
37 str r1, [r0]
38
39 /*
40 * pll clock initialization predefined in apf27.h
41 */
42 write32 MPCTL0, ACFG_MPCTL0_VAL
43 write32 SPCTL0, ACFG_SPCTL0_VAL
44
45 write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
46
47 /*
48 * add some delay here
49 */
50 mov r1, #0x1000
51 1: subs r1, r1, #0x1
52 bne 1b
53
54 /* peripheral clock divider */
55 write32 PCDR0, ACFG_PCDR0_VAL
56 write32 PCDR1, ACFG_PCDR1_VAL
57
58 /* Configure PCCR0 and PCCR1 */
59 write32 PCCR0, ACFG_PCCR0_VAL
60 write32 PCCR1, ACFG_PCCR1_VAL
61
62 .endm /* init_clock */
63
64 .macro init_ddr
65 /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
66 ldr r0, =IMX_ESD_BASE
67 ldr r4, =ESDMISC_SDRAM_RDY
682: ldr r1, [r0, #ESDMISC_ROF]
69 ands r1, r1, r4
70 bpl 2b
71
72 /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
73 ldr r0, =IMX_ESD_BASE
74 ldr r4, =ACFG_ESDMISC_VAL
75 orr r1, r4, #ESDMISC_MDDR_DL_RST
76 str r1, [r0, #ESDMISC_ROF]
77
78 /* Hold for more than 200ns */
79 ldr r1, =0x10000
801: subs r1, r1, #0x1
81 bne 1b
82
83 str r4, [r0]
84
85 ldr r0, =IMX_ESD_BASE
86 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
87 str r1, [r0, #ESDCFG0_ROF]
88
89 ldr r0, =IMX_ESD_BASE
90 ldr r1, =ACFG_PRECHARGE_CMD
91 str r1, [r0, #ESDCTL0_ROF]
92
93 /* write8(0xA0001000, any value) */
94 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
95 strb r2, [r1]
96
97 ldr r1, =ACFG_AUTOREFRESH_CMD
98 str r1, [r0, #ESDCTL0_ROF]
99
100 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
101
102 ldr r6,=0x7 /* load loop counter */
1031: str r5,[r4] /* run auto-refresh cycle to array 0 */
104 subs r6,r6,#1
105 bne 1b
106
107 ldr r1, =ACFG_SET_MODE_REG_CMD
108 str r1, [r0, #ESDCTL0_ROF]
109
110 /* set standard mode register */
111 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
112 strb r2, [r4]
113
114 /* set extended mode register */
115 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
116 strb r5, [r4]
117
118 ldr r1, =ACFG_NORMAL_RW_CMD
119 str r1, [r0, #ESDCTL0_ROF]
120
121 /* 2nd sdram */
122 ldr r0, =IMX_ESD_BASE
123 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
124 str r1, [r0, #ESDCFG1_ROF]
125
126 ldr r0, =IMX_ESD_BASE
127 ldr r1, =ACFG_PRECHARGE_CMD
128 str r1, [r0, #ESDCTL1_ROF]
129
130 /* write8(0xB0001000, any value) */
131 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
132 strb r2, [r1]
133
134 ldr r1, =ACFG_AUTOREFRESH_CMD
135 str r1, [r0, #ESDCTL1_ROF]
136
137 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
138
139 ldr r6,=0x7 /* load loop counter */
1401: str r5,[r4] /* run auto-refresh cycle to array 0 */
141 subs r6,r6,#1
142 bne 1b
143
144 ldr r1, =ACFG_SET_MODE_REG_CMD
145 str r1, [r0, #ESDCTL1_ROF]
146
147 /* set standard mode register */
148 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
149 strb r2, [r4]
150
151 /* set extended mode register */
152 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
153 strb r2, [r4]
154
155 ldr r1, =ACFG_NORMAL_RW_CMD
156 str r1, [r0, #ESDCTL1_ROF]
157 .endm /* init_ddr */
158
159.globl lowlevel_init
160lowlevel_init:
161
162 init_aipi
163 init_clock
164#ifdef CONFIG_SPL_BUILD
165 init_ddr
166#endif
167
168 mov pc, lr