| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 1 | #ifndef __ASM_SH_CACHE_H |
| 2 | #define __ASM_SH_CACHE_H |
| 3 | |
| Masahiro Yamada | 7d23666 | 2014-11-06 15:55:21 +0900 | [diff] [blame] | 4 | #if defined(CONFIG_CPU_SH4) |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 5 | |
| 6 | #define L1_CACHE_BYTES 32 |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 7 | |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 8 | struct __large_struct { unsigned long buf[100]; }; |
| 9 | #define __m(x) (*(struct __large_struct *)(x)) |
| 10 | |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 11 | #else |
| 12 | |
| 13 | /* |
| 14 | * 32-bytes is the largest L1 data cache line size for SH the architecture. So |
| 15 | * it is a safe default for DMA alignment. |
| 16 | */ |
| 17 | #define ARCH_DMA_MINALIGN 32 |
| 18 | |
| Masahiro Yamada | 7d23666 | 2014-11-06 15:55:21 +0900 | [diff] [blame] | 19 | #endif /* CONFIG_CPU_SH4 */ |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 20 | |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 21 | /* |
| 22 | * Use the L1 data cache line size value for the minimum DMA buffer alignment |
| 23 | * on SH. |
| 24 | */ |
| 25 | #ifndef ARCH_DMA_MINALIGN |
| 26 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| 27 | #endif |
| 28 | |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 29 | #endif /* __ASM_SH_CACHE_H */ |