blob: 239b671ac38156755a308720aadacd7619d5b66c [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard40d1a312017-09-05 11:04:24 +02002/*
3 * STiH407 family DWC3 specific Glue layer
4 *
Patrice Chotardfb48bc42017-10-23 09:53:57 +02005 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard0f8106f2020-12-02 18:47:30 +01006 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotard40d1a312017-09-05 11:04:24 +02007 */
8
9#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Simon Glass401d1c42020-10-30 21:38:53 -060011#include <asm/global_data.h>
Patrice Chotard40d1a312017-09-05 11:04:24 +020012#include <asm/io.h>
13#include <dm.h>
14#include <errno.h>
Patrice Chotard40d1a312017-09-05 11:04:24 +020015#include <dm/lists.h>
16#include <regmap.h>
17#include <reset-uclass.h>
18#include <syscon.h>
19#include <usb.h>
20
21#include <linux/usb/dwc3.h>
22#include <linux/usb/otg.h>
23#include <dwc3-sti-glue.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27/*
Simon Glass8a8d24b2020-12-03 16:55:23 -070028 * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
Patrice Chotard40d1a312017-09-05 11:04:24 +020029 * @syscfg_base: addr for the glue syscfg
30 * @glue_base: addr for the glue registers
31 * @syscfg_offset: usb syscfg control offset
32 * @powerdown_ctl: rest controller for powerdown signal
33 * @softreset_ctl: reset controller for softreset signal
34 * @mode: drd static host/device config
35 */
Simon Glass8a8d24b2020-12-03 16:55:23 -070036struct sti_dwc3_glue_plat {
Patrice Chotard40d1a312017-09-05 11:04:24 +020037 phys_addr_t syscfg_base;
38 phys_addr_t glue_base;
39 phys_addr_t syscfg_offset;
40 struct reset_ctl powerdown_ctl;
41 struct reset_ctl softreset_ctl;
42 enum usb_dr_mode mode;
43};
44
Simon Glass8a8d24b2020-12-03 16:55:23 -070045static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotard40d1a312017-09-05 11:04:24 +020046{
47 unsigned long val;
48
49 val = readl(plat->syscfg_base + plat->syscfg_offset);
50
51 val &= USB3_CONTROL_MASK;
52
53 switch (plat->mode) {
54 case USB_DR_MODE_PERIPHERAL:
55 val &= ~(USB3_DELAY_VBUSVALID
56 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
57 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
58 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
59
60 val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
61 break;
62
63 case USB_DR_MODE_HOST:
64 val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
65 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
66 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
67 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
68
69 val |= USB3_DELAY_VBUSVALID;
70 break;
71
72 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +090073 pr_err("Unsupported mode of operation %d\n", plat->mode);
Patrice Chotard40d1a312017-09-05 11:04:24 +020074 return -EINVAL;
75 }
76 writel(val, plat->syscfg_base + plat->syscfg_offset);
77
78 return 0;
79}
80
Simon Glass8a8d24b2020-12-03 16:55:23 -070081static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotard40d1a312017-09-05 11:04:24 +020082{
83 unsigned long reg;
84
85 reg = readl(plat->glue_base + CLKRST_CTRL);
86
87 reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
88 reg &= ~SW_PIPEW_RESET_N;
89
90 writel(reg, plat->glue_base + CLKRST_CTRL);
91
92 /* configure mux for vbus, powerpresent and bvalid signals */
93 reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
94
95 reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
96 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
97 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
98
99 writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
100
101 setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
102}
103
Simon Glassd1998a92020-12-03 16:55:21 -0700104static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
Patrice Chotard40d1a312017-09-05 11:04:24 +0200105{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700106 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200107 struct udevice *syscon;
108 struct regmap *regmap;
109 int ret;
110 u32 reg[4];
111
Simon Glassf10643c2020-12-19 10:40:14 -0700112 ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg,
113 ARRAY_SIZE(reg));
Patrice Chotard40d1a312017-09-05 11:04:24 +0200114 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900115 pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200116 return ret;
117 }
118
119 plat->glue_base = reg[0];
120 plat->syscfg_offset = reg[2];
121
122 /* get corresponding syscon phandle */
123 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg",
124 &syscon);
125 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900126 pr_err("unable to find syscon device (%d)\n", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200127 return ret;
128 }
129
130 /* get syscfg-reg base address */
131 regmap = syscon_get_regmap(syscon);
132 if (!regmap) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900133 pr_err("unable to find regmap\n");
Patrice Chotard40d1a312017-09-05 11:04:24 +0200134 return -ENODEV;
135 }
Masahiro Yamada8c1de5e2018-04-19 12:14:01 +0900136 plat->syscfg_base = regmap->ranges[0].start;
Patrice Chotard40d1a312017-09-05 11:04:24 +0200137
138 /* get powerdown reset */
139 ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
140 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900141 pr_err("can't get powerdown reset for %s (%d)", dev->name, ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200142 return ret;
143 }
144
145 /* get softreset reset */
146 ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
147 if (ret)
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900148 pr_err("can't get soft reset for %s (%d)", dev->name, ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200149
150 return ret;
151};
152
153static int sti_dwc3_glue_bind(struct udevice *dev)
154{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700155 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Kever Yangac28e592020-03-04 08:59:50 +0800156 ofnode node, dwc3_node;
Patrice Chotard40d1a312017-09-05 11:04:24 +0200157
Kever Yangac28e592020-03-04 08:59:50 +0800158 /* Find snps,dwc3 node from subnode */
Simon Glassf10643c2020-12-19 10:40:14 -0700159 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
Kever Yangac28e592020-03-04 08:59:50 +0800160 if (ofnode_device_is_compatible(node, "snps,dwc3"))
161 dwc3_node = node;
Patrice Chotard40d1a312017-09-05 11:04:24 +0200162 }
163
Patrice Chotardf3858ce2020-06-29 11:19:02 +0200164 if (!ofnode_valid(dwc3_node)) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900165 pr_err("Can't find dwc3 subnode for %s\n", dev->name);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200166 return -ENODEV;
167 }
168
169 /* retrieve the DWC3 dual role mode */
170 plat->mode = usb_get_dr_mode(dwc3_node);
171 if (plat->mode == USB_DR_MODE_UNKNOWN)
172 /* by default set dual role mode to HOST */
173 plat->mode = USB_DR_MODE_HOST;
174
175 return dm_scan_fdt_dev(dev);
176}
177
178static int sti_dwc3_glue_probe(struct udevice *dev)
179{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700180 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200181 int ret;
182
183 /* deassert both powerdown and softreset */
184 ret = reset_deassert(&plat->powerdown_ctl);
185 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900186 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200187 return ret;
188 }
189
190 ret = reset_deassert(&plat->softreset_ctl);
191 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900192 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200193 goto softreset_err;
194 }
195
196 ret = sti_dwc3_glue_drd_init(plat);
197 if (ret)
198 goto init_err;
199
200 sti_dwc3_glue_init(plat);
201
202 return 0;
203
204init_err:
205 ret = reset_assert(&plat->softreset_ctl);
206 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900207 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200208 return ret;
209 }
210
211softreset_err:
212 ret = reset_assert(&plat->powerdown_ctl);
213 if (ret < 0)
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900214 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200215
216 return ret;
217}
218
219static int sti_dwc3_glue_remove(struct udevice *dev)
220{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700221 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200222 int ret;
223
224 /* assert both powerdown and softreset */
225 ret = reset_assert(&plat->powerdown_ctl);
226 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900227 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200228 return ret;
229 }
230
231 ret = reset_assert(&plat->softreset_ctl);
232 if (ret < 0)
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900233 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotard40d1a312017-09-05 11:04:24 +0200234
235 return ret;
236}
237
238static const struct udevice_id sti_dwc3_glue_ids[] = {
239 { .compatible = "st,stih407-dwc3" },
240 { }
241};
242
243U_BOOT_DRIVER(dwc3_sti_glue) = {
244 .name = "dwc3_sti_glue",
Patrice Chotardf3bc7362020-04-28 13:49:50 +0200245 .id = UCLASS_NOP,
Patrice Chotard40d1a312017-09-05 11:04:24 +0200246 .of_match = sti_dwc3_glue_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700247 .of_to_plat = sti_dwc3_glue_of_to_plat,
Patrice Chotard40d1a312017-09-05 11:04:24 +0200248 .probe = sti_dwc3_glue_probe,
249 .remove = sti_dwc3_glue_remove,
250 .bind = sti_dwc3_glue_bind,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700251 .plat_auto = sizeof(struct sti_dwc3_glue_plat),
Patrice Chotard40d1a312017-09-05 11:04:24 +0200252 .flags = DM_FLAG_ALLOC_PRIV_DMA,
253};