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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
wdenk8bde7f72003-06-27 21:31:46 +000025#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000026#include "w7o.h"
27#include <asm/processor.h>
28
29#include "vpd.h"
30#include "errors.h"
31#include <watchdog.h>
32
wdenkc83bf6a2004-01-06 22:38:14 +000033unsigned long get_dram_size (void);
wdenkc6097192002-11-03 00:24:07 +000034
35/*
36 * Macros to transform values
37 * into environment strings.
38 */
39#define XMK_STR(x) #x
40#define MK_STR(x) XMK_STR(x)
41
42/* ------------------------------------------------------------------------- */
43
wdenkc837dcb2004-01-20 23:12:12 +000044int board_early_init_f (void)
wdenkc6097192002-11-03 00:24:07 +000045{
46#if defined(CONFIG_W7OLMG)
wdenkc83bf6a2004-01-06 22:38:14 +000047 /*
48 * Setup GPIO pins - reset devices.
49 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020050 out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
51 out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
52 out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
wdenkc6097192002-11-03 00:24:07 +000053
wdenkc83bf6a2004-01-06 22:38:14 +000054 /*
55 * IRQ 0-15 405GP internally generated; active high; level sensitive
56 * IRQ 16 405GP internally generated; active low; level sensitive
57 * IRQ 17-24 RESERVED
58 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
59 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
60 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
61 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
62 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
63 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
64 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
65 */
66 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
67 mtdcr (uicer, 0x00000000); /* disable all ints */
wdenkc6097192002-11-03 00:24:07 +000068
wdenkc83bf6a2004-01-06 22:38:14 +000069 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
70 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
71 mtdcr (uictr, 0x10000000); /* set int trigger levels */
72 mtdcr (uicvcr, 0x00000001); /* set vect base=0,
73 INT0 highest priority */
wdenkc6097192002-11-03 00:24:07 +000074
wdenkc83bf6a2004-01-06 22:38:14 +000075 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
wdenkc6097192002-11-03 00:24:07 +000076
77#elif defined(CONFIG_W7OLMC)
wdenkc83bf6a2004-01-06 22:38:14 +000078 /*
79 * Setup GPIO pins
80 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020081 out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
82 out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
83 out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
wdenkc6097192002-11-03 00:24:07 +000084
wdenkc83bf6a2004-01-06 22:38:14 +000085 /*
86 * IRQ 0-15 405GP internally generated; active high; level sensitive
87 * IRQ 16 405GP internally generated; active low; level sensitive
88 * IRQ 17-24 RESERVED
89 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
90 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
91 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
92 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
93 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
94 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
95 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
96 */
97 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
98 mtdcr (uicer, 0x00000000); /* disable all ints */
wdenkc6097192002-11-03 00:24:07 +000099
wdenkc83bf6a2004-01-06 22:38:14 +0000100 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
101 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
102 mtdcr (uictr, 0x10000000); /* set int trigger levels */
103 mtdcr (uicvcr, 0x00000001); /* set vect base=0,
104 INT0 highest priority */
wdenkc6097192002-11-03 00:24:07 +0000105
wdenkc83bf6a2004-01-06 22:38:14 +0000106 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
wdenkc6097192002-11-03 00:24:07 +0000107
wdenkc83bf6a2004-01-06 22:38:14 +0000108#else /* Unknown */
wdenkc6097192002-11-03 00:24:07 +0000109# error "Unknown W7O board configuration"
110#endif
111
wdenkc83bf6a2004-01-06 22:38:14 +0000112 WATCHDOG_RESET (); /* Reset the watchdog */
113 temp_uart_init (); /* init the uart for debug */
114 WATCHDOG_RESET (); /* Reset the watchdog */
115 test_led (); /* test the LEDs */
116 test_sdram (get_dram_size ()); /* test the dram */
117 log_stat (ERR_POST1); /* log status,post1 complete */
118 return 0;
wdenkc6097192002-11-03 00:24:07 +0000119}
120
121
122/* ------------------------------------------------------------------------- */
123
124/*
125 * Check Board Identity:
126 */
127int checkboard (void)
128{
wdenkc83bf6a2004-01-06 22:38:14 +0000129 VPD vpd;
wdenkc6097192002-11-03 00:24:07 +0000130
wdenkc83bf6a2004-01-06 22:38:14 +0000131 puts ("Board: ");
wdenkc6097192002-11-03 00:24:07 +0000132
wdenkc83bf6a2004-01-06 22:38:14 +0000133 /* VPD data present in I2C EEPROM */
134 if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
135 /*
136 * Known board type.
137 */
138 if (vpd.productId[0] &&
139 ((strncmp (vpd.productId, "GMM", 3) == 0) ||
140 (strncmp (vpd.productId, "CMM", 3) == 0))) {
wdenkc6097192002-11-03 00:24:07 +0000141
wdenkc83bf6a2004-01-06 22:38:14 +0000142 /* Output board information on startup */
143 printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
144 return (0);
145 }
wdenkc6097192002-11-03 00:24:07 +0000146 }
wdenkc6097192002-11-03 00:24:07 +0000147
wdenkc83bf6a2004-01-06 22:38:14 +0000148 puts ("### Unknown HW ID - assuming NOTHING\n");
149 return (0);
wdenkc6097192002-11-03 00:24:07 +0000150}
151
152/* ------------------------------------------------------------------------- */
153
154long int initdram (int board_type)
155{
wdenkc83bf6a2004-01-06 22:38:14 +0000156 return get_dram_size ();
wdenkc6097192002-11-03 00:24:07 +0000157}
158
159unsigned long get_dram_size (void)
160{
wdenkc83bf6a2004-01-06 22:38:14 +0000161 int tmp, i, regs[4];
162 int size = 0;
wdenkc6097192002-11-03 00:24:07 +0000163
wdenkc83bf6a2004-01-06 22:38:14 +0000164 /* Get bank Size registers */
165 mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */
166 regs[0] = mfdcr (memcfgd);
wdenkc6097192002-11-03 00:24:07 +0000167
wdenkc83bf6a2004-01-06 22:38:14 +0000168 mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */
169 regs[1] = mfdcr (memcfgd);
wdenkc6097192002-11-03 00:24:07 +0000170
wdenkc83bf6a2004-01-06 22:38:14 +0000171 mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */
172 regs[2] = mfdcr (memcfgd);
wdenkc6097192002-11-03 00:24:07 +0000173
wdenkc83bf6a2004-01-06 22:38:14 +0000174 mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */
175 regs[3] = mfdcr (memcfgd);
wdenkc6097192002-11-03 00:24:07 +0000176
wdenkc83bf6a2004-01-06 22:38:14 +0000177 /* compute the size, add each bank if enabled */
178 for (i = 0; i < 4; i++) {
179 if (regs[i] & 0x0001) { /* if enabled, */
180 tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
181 tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
182 size += tmp;
183 }
wdenkc6097192002-11-03 00:24:07 +0000184 }
wdenkc6097192002-11-03 00:24:07 +0000185
wdenkc83bf6a2004-01-06 22:38:14 +0000186 return size;
wdenkc6097192002-11-03 00:24:07 +0000187}
188
189int misc_init_f (void)
190{
wdenkc83bf6a2004-01-06 22:38:14 +0000191 return 0;
wdenkc6097192002-11-03 00:24:07 +0000192}
193
wdenkc83bf6a2004-01-06 22:38:14 +0000194static void w7o_env_init (VPD * vpd)
wdenkc6097192002-11-03 00:24:07 +0000195{
wdenkc83bf6a2004-01-06 22:38:14 +0000196 /*
197 * Read VPD
198 */
199 if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0)
200 return;
wdenkc6097192002-11-03 00:24:07 +0000201
wdenkc83bf6a2004-01-06 22:38:14 +0000202 /*
203 * Known board type.
204 */
205 if (vpd->productId[0] &&
206 ((strncmp (vpd->productId, "GMM", 3) == 0) ||
207 (strncmp (vpd->productId, "CMM", 3) == 0))) {
208 char buf[30];
209 char *eth;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200210 char *serial = getenv ("serial#");
211 char *ethaddr = getenv ("ethaddr");
wdenkc6097192002-11-03 00:24:07 +0000212
wdenkc83bf6a2004-01-06 22:38:14 +0000213 /* Set 'serial#' envvar if serial# isn't set */
214 if (!serial) {
215 sprintf (buf, "%s-%ld", vpd->productId,
216 vpd->serialNum);
217 setenv ("serial#", buf);
218 }
219
220 /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200221 eth = (char *)(vpd->ethAddrs[0]);
wdenkc83bf6a2004-01-06 22:38:14 +0000222 if (ethaddr
223 && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
224 /* Now setup ethaddr */
225 sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
226 eth[0], eth[1], eth[2], eth[3], eth[4],
227 eth[5]);
228 setenv ("ethaddr", buf);
229 }
wdenkc6097192002-11-03 00:24:07 +0000230 }
wdenkc83bf6a2004-01-06 22:38:14 +0000231} /* w7o_env_init() */
wdenkc6097192002-11-03 00:24:07 +0000232
233
234int misc_init_r (void)
235{
wdenkc83bf6a2004-01-06 22:38:14 +0000236 VPD vpd; /* VPD information */
wdenkc6097192002-11-03 00:24:07 +0000237
238#if defined(CONFIG_W7OLMG)
wdenkc83bf6a2004-01-06 22:38:14 +0000239 unsigned long greg; /* GPIO Register */
wdenkc6097192002-11-03 00:24:07 +0000240
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200241 greg = in32 (PPC405GP_GPIO0_OR);
wdenkc6097192002-11-03 00:24:07 +0000242
wdenkc83bf6a2004-01-06 22:38:14 +0000243 /*
244 * XXX - Unreset devices - this should be moved into VxWorks driver code
245 */
246 greg |= 0x41800000L; /* SAM, PHY, Galileo */
wdenkc6097192002-11-03 00:24:07 +0000247
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200248 out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
wdenkc6097192002-11-03 00:24:07 +0000249#endif /* CONFIG_W7OLMG */
250
wdenkc83bf6a2004-01-06 22:38:14 +0000251 /*
252 * Initialize W7O environment variables
253 */
254 w7o_env_init (&vpd);
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc83bf6a2004-01-06 22:38:14 +0000256 /*
257 * Initialize the FPGA(s).
258 */
259 if (init_fpga () == 0)
260 test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
wdenkc6097192002-11-03 00:24:07 +0000261
wdenkc83bf6a2004-01-06 22:38:14 +0000262 /* More POST testing. */
263 post2 ();
wdenkc6097192002-11-03 00:24:07 +0000264
wdenkc83bf6a2004-01-06 22:38:14 +0000265 /* Done with hardware initialization and POST. */
266 log_stat (ERR_POSTOK);
wdenkc6097192002-11-03 00:24:07 +0000267
wdenkc83bf6a2004-01-06 22:38:14 +0000268 /* Call silly, fail safe boot init routine */
269 init_fsboot ();
wdenkc6097192002-11-03 00:24:07 +0000270
271 return (0);
272}