| wdenk | 2d24a3a | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004 Arabella Software Ltd. |
| 3 | * Yuli Barcohen <yuli@arabellasw.com> |
| 4 | * |
| 5 | * Support for Analogue&Micro Adder boards family. |
| 6 | * Tested on AdderII and Adder87x. |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <common.h> |
| 28 | #include <mpc8xx.h> |
| 29 | |
| 30 | /* |
| 31 | * SDRAM is single Samsung K4S643232F-T70 chip. |
| 32 | * Minimal CPU frequency is 40MHz. |
| 33 | */ |
| 34 | static uint sdram_table[] = { |
| 35 | /* Single read (offset 0x00 in UPM RAM) */ |
| 36 | 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, |
| 37 | 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, |
| 38 | |
| 39 | /* Burst read (offset 0x08 in UPM RAM) */ |
| 40 | 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, |
| 41 | 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, |
| 42 | 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, |
| 43 | 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, |
| 44 | |
| 45 | /* Single write (offset 0x18 in UPM RAM) */ |
| 46 | 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, |
| 47 | 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 48 | |
| 49 | /* Burst write (offset 0x20 in UPM RAM) */ |
| 50 | 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, |
| 51 | 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, |
| 52 | 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 53 | 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 54 | |
| 55 | /* Refresh (offset 0x30 in UPM RAM) */ |
| 56 | 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 57 | 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, |
| 58 | 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 59 | |
| 60 | /* Exception (offset 0x3C in UPM RAM) */ |
| 61 | 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 |
| 62 | }; |
| 63 | |
| 64 | long int initdram (int board_type) |
| 65 | { |
| 66 | long int msize = CFG_SDRAM_SIZE; |
| 67 | volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; |
| 68 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 69 | |
| 70 | upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); |
| 71 | |
| 72 | /* Configure SDRAM refresh */ |
| 73 | memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ |
| 74 | |
| 75 | memctl->memc_mamr = (94 << 24) | CFG_MAMR; |
| 76 | memctl->memc_mar = 0x0; |
| 77 | udelay(200); |
| 78 | |
| 79 | /* Run precharge from location 0x15 */ |
| 80 | memctl->memc_mcr = 0x80002115; |
| 81 | udelay(200); |
| 82 | |
| 83 | /* Run 8 refresh cycles */ |
| 84 | memctl->memc_mcr = 0x80002830; |
| 85 | udelay(200); |
| 86 | |
| 87 | memctl->memc_mar = 0x88; |
| 88 | udelay(200); |
| 89 | |
| 90 | /* Run MRS pattern from location 0x16 */ |
| 91 | memctl->memc_mcr = 0x80002116; |
| 92 | udelay(200); |
| 93 | |
| 94 | return msize; |
| 95 | } |
| 96 | |
| 97 | int checkboard( void ) |
| 98 | { |
| 99 | puts("Board: Adder"); |
| 100 | #if defined(CONFIG_MPC885_FAMILY) |
| 101 | puts("87x\n"); |
| 102 | #elif defined(CONFIG_MPC866_FAMILY) |
| 103 | puts("II\n"); |
| 104 | #endif |
| 105 | |
| 106 | return 0; |
| 107 | } |