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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7521af1c7d95ff087a4f7636ed050f4d4be91b59 / . / board / amirix / ap1000 / ap1000.h
blob: c93736f4285920f70032e7b51a0776970741faed [file] [log] [blame]
Wolfgang Denk7521af12005-10-09 01:04:33 +0200[diff] [blame^]1/*
2 * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
3 *
4 * Author : James MacAulay
5 *
6 * This software may be used and distributed according to the terms of
7 * the GNU General Public License (GPL) version 2, incorporated herein by
8 * reference. Drivers based on or derived from this code fall under the GPL
9 * and must retain the authorship, copyright and this license notice. This
10 * file is not a complete program and may only be used when the entire
11 * program is licensed under the GPL.
12 *
13 */
14
15#ifndef __AP1000_H
16#define __AP1000_H
17
18/*
19 * Revision Register stuff
20 */
21#define AP1xx_FPGA_REV_ADDR 0x29000000
22
23#define AP1xx_PLATFORM_MASK 0xFF000000
24#define AP100_BASELINE_PLATFORM 0x01000000
25#define AP1xx_QUADGE_PLATFORM 0x02000000
26#define AP1xx_MGT_REF_PLATFORM 0x03000000
27#define AP1xx_STANDARD_PLATFORM 0x04000000
28#define AP1xx_DUAL_PLATFORM 0x05000000
29#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
30
31#define AP1000_BASELINE_PLATFORM 0x21000000
32
33#define AP1xx_TESTPLATFORM_MASK 0xC0000000
34#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
35#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
36#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
37
38#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
39
40#define AP1xx_TARGET_MASK 0x00FF0000
41#define AP1xx_AP107_TARGET 0x00010000
42#define AP1xx_AP120_TARGET 0x00020000
43#define AP1xx_AP130_TARGET 0x00030000
44#define AP1xx_AP1070_TARGET 0x00040000
45#define AP1xx_AP1100_TARGET 0x00050000
46
47#define AP1xx_UNKNOWN_STR "Unknown"
48
49#define AP1xx_PLATFORM_STR " Platform"
50#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
51#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
52#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
53#define AP1xx_STANDARD_PLATFORM_STR "Standard"
54#define AP1xx_DUAL_PLATFORM_STR "Dual"
55#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
56
57#define AP1xx_TESTPLATFORM_STR " Test Platform"
58#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
59#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
60#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
61
62#define AP1xx_TARGET_STR " Board"
63#define AP1xx_AP107_TARGET_STR "AP107"
64#define AP1xx_AP120_TARGET_STR "AP120"
65#define AP1xx_AP130_TARGET_STR "AP130"
66
67#define AP1xx_AP1070_TARGET_STR "AP1070"
68#define AP1xx_AP1100_TARGET_STR "AP1100"
69
70/*
71 * Flash Stuff
72 */
73#define AP1xx_PROGRAM_FLASH_INDEX 0
74#define AP1xx_CONFIG_FLASH_INDEX 1
75
76/*
77 * System Ace Stuff
78 */
79#define AP1000_SYSACE_REGBASE 0x28000000
80
81#define SYSACE_STATREG0 0x04 // 7:0
82#define SYSACE_STATREG1 0x05 // 15:8
83#define SYSACE_STATREG2 0x06 // 23:16
84#define SYSACE_STATREG3 0x07 // 31:24
85
86#define SYSACE_ERRREG0 0x08 // 7:0
87#define SYSACE_ERRREG1 0x09 // 15:8
88#define SYSACE_ERRREG2 0x0a // 23:16
89#define SYSACE_ERRREG3 0x0b // 31:24
90
91#define SYSACE_CTRLREG0 0x18 // 7:0
92#define SYSACE_CTRLREG1 0x19 // 15:8
93#define SYSACE_CTRLREG2 0x1A // 23:16
94#define SYSACE_CTRLREG3 0x1B // 31:24
95
96/*
97 * Software reconfig thing
98 */
99#define SW_BYTE_SECTOR_ADDR 0x24FE0000
100#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
101#define SW_BYTE_SECTOR_SIZE 0x00020000
102#define SW_BYTE_MASK 0x00000003
103
104#define DEFAULT_TEMP_ADDR 0x00100000
105
106#define AP1000_CPLD_BASE 0x26000000
107
108/* PowerSpan II Stuff */
109#define PSII_SYNC() asm("eieio")
110#define PSPAN_BASEADDR 0x30000000
111#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
112 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
113 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
114 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
115 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
116 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
117 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
118 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
119 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
120 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
121 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
122 0x00, /* Byte 15 - Vital Product Data Disabled. */ \
123 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
124 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
125 0x00, /* Byte 18 - I2O disabled */ \
126 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
127 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
128 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
129 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
130 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
131 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
132 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
133 /* Long Load Information */ \
134 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
135 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
136 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
137 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
138 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
139 0x01, /* Byte 39 - Power span revision 1. */ \
140 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
141 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
142 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
143 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
144 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
145 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
146 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
147 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
148 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
149 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
150 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
151 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
152 0x01, /* Byte 59 - PCI-2 class revision 1 */ \
153 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
154
155
156#define EEPROM_LENGTH 64 /* Long Load */
157
158#define I2C_SENSOR_DEV 0x9
159#define I2C_SENSOR_CHIP_SEL 0x4
160
161/*
162 * Board Functions
163 */
164void set_eat_machine_checks(int a_flag);
165int get_eat_machine_checks(void);
166unsigned int get_platform(void);
167unsigned int get_device(void);
168void* memcpyb(void * dest,const void *src,size_t count);
169int process_bootflag(ulong bootflag);
170void user_led_on(void);
171void user_led_off(void);
172
173#endif /* __COMMON_H_ */