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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7521af1c7d95ff087a4f7636ed050f4d4be91b59 / . / board / tqm8560 / tqm8560.c
blob: 71f58805bc28aa6df90df061ec14734cb8b5bdcf [file] [log] [blame]
wdenkf5c5ef42005-04-05 16:26:47 +0000[diff] [blame]1/*
2 * Copyright 2005 DENX Software Engineering
3 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002,2003, Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28
29#include <common.h>
30#include <pci.h>
31#include <asm/processor.h>
32#include <asm/immap_85xx.h>
33#include <ioports.h>
34#include <spd.h>
35
36#if defined(CONFIG_DDR_ECC)
37extern void ddr_enable_ecc (unsigned int dram_size);
38#endif
39
40extern long int spd_sdram (void);
41
42void local_bus_init (void);
43long int fixed_sdram (void);
44
45/*
46 * I/O Port configuration table
47 *
48 * if conf is 1, then that port pin will be configured at boot time
49 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 */
51
52const iop_conf_t iop_conf_tab[4][32] = {
53
54 /* Port A configuration */
55 { /* conf ppar psor pdir podr pdat */
56 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
57 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
58 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
59 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
60 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
61 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
66 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
67 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
68 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
69 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
70 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
71 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
72 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
73 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
86 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 },
89
90 /* Port B configuration */
91 { /* conf ppar psor pdir podr pdat */
92 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
93 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
94 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
95 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
96 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
97 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
98 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
99 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
100 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
101 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
102 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
103 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
104 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
105 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
106 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
107 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
108 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
109 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
110 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
111 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
112 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 },
125
126 /* Port C */
127 { /* conf ppar psor pdir podr pdat */
128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
138 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
139 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
140 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
142 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
143 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
144 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
146 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
149 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
150 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
160 },
161
162 /* Port D */
163 { /* conf ppar psor pdir podr pdat */
164 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
165 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
166 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
167 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
168 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
169 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 }
197};
198
199
200int board_early_init_f (void)
201{
202 return 0;
203}
204
205int checkboard (void)
206{
207 puts ("Board: TQM8560\n");
208
209#ifdef CONFIG_PCI
210 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
211 CONFIG_SYS_CLK_FREQ / 1000000);
212#else
213 printf ("PCI1: disabled\n");
214#endif
215 /*
216 * Initialize local bus.
217 */
218 local_bus_init ();
219
220 return 0;
221}
222
223
224long int initdram (int board_type)
225{
226 long dram_size = 0;
227 extern long spd_sdram (void);
228 volatile immap_t *immap = (immap_t *) CFG_IMMR;
229
230#if defined(CONFIG_DDR_DLL)
231 {
Stefan Roese9d2a8732005-08-31 12:55:50 +0200[diff] [blame]232 volatile ccsr_gur_t *gur= &immap->im_gur;
233 int i,x;
234
235 x = 10;
wdenkf5c5ef42005-04-05 16:26:47 +0000[diff] [blame]236
237 /*
238 * Work around to stabilize DDR DLL
239 */
Stefan Roese9d2a8732005-08-31 12:55:50 +0200[diff] [blame]240 gur->ddrdllcr = 0x81000000;
241 asm("sync;isync;msync");
242 udelay (200);
243 while (gur->ddrdllcr != 0x81000100) {
244 gur->devdisr = gur->devdisr | 0x00010000;
245 asm("sync;isync;msync");
246 for (i=0; i<x; i++)
247 ;
248 gur->devdisr = gur->devdisr & 0xfff7ffff;
249 asm("sync;isync;msync");
250 x++;
251 }
wdenkf5c5ef42005-04-05 16:26:47 +0000[diff] [blame]252 }
253#endif
254
255#if defined(CONFIG_SPD_EEPROM)
256 dram_size = spd_sdram ();
257#else
258 dram_size = fixed_sdram ();
259#endif
260
261#if defined(CONFIG_DDR_ECC)
262 /*
263 * Initialize and enable DDR ECC.
264 */
265 ddr_enable_ecc (dram_size);
266#endif
267
268 return dram_size;
269}
270
271
272/*
273 * Initialize Local Bus
274 */
275
276void local_bus_init (void)
277{
278 volatile immap_t *immap = (immap_t *) CFG_IMMR;
279 volatile ccsr_gur_t *gur = &immap->im_gur;
280 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
281
282 uint clkdiv;
283 uint lbc_hz;
284 sys_info_t sysinfo;
285
286 /*
287 * Errata LBC11.
288 * Fix Local Bus clock glitch when DLL is enabled.
289 *
290 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
291 * If localbus freq is > 133Mhz, DLL can be safely enabled.
292 * Between 66 and 133, the DLL is enabled with an override workaround.
293 */
294
295 get_sys_info (&sysinfo);
296 clkdiv = lbc->lcrr & 0x0f;
297 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
298
299 if (lbc_hz < 66) {
300 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
301 lbc->ltedr = 0xa4c80000; /* DK: !!! */
302
303 } else if (lbc_hz >= 133) {
304 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
305
306 } else {
307 /*
308 * On REV1 boards, need to change CLKDIV before enable DLL.
309 * Default CLKDIV is 8, change it to 4 temporarily.
310 */
311 uint pvr = get_pvr ();
312 uint temp_lbcdll = 0;
313
314 if (pvr == PVR_85xx_REV1) {
315 /* FIXME: Justify the high bit here. */
316 lbc->lcrr = 0x10000004;
317 }
318
319 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
320 udelay (200);
321
322 /*
323 * Sample LBC DLL ctrl reg, upshift it to set the
324 * override bits.
325 */
326 temp_lbcdll = gur->lbcdllcr;
327 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
328 asm ("sync;isync;msync");
329 }
330}
331
332
333#if defined(CFG_DRAM_TEST)
334int testdram (void)
335{
336 uint *pstart = (uint *) CFG_MEMTEST_START;
337 uint *pend = (uint *) CFG_MEMTEST_END;
338 uint *p;
339
340 printf ("SDRAM test phase 1:\n");
341 for (p = pstart; p < pend; p++)
342 *p = 0xaaaaaaaa;
343
344 for (p = pstart; p < pend; p++) {
345 if (*p != 0xaaaaaaaa) {
346 printf ("SDRAM test fails at: %08x\n", (uint) p);
347 return 1;
348 }
349 }
350
351 printf ("SDRAM test phase 2:\n");
352 for (p = pstart; p < pend; p++)
353 *p = 0x55555555;
354
355 for (p = pstart; p < pend; p++) {
356 if (*p != 0x55555555) {
357 printf ("SDRAM test fails at: %08x\n", (uint) p);
358 return 1;
359 }
360 }
361
362 printf ("SDRAM test passed.\n");
363 return 0;
364}
365#endif
366
367
368#if !defined(CONFIG_SPD_EEPROM)
369/*************************************************************************
370 * fixed sdram init -- doesn't use serial presence detect.
371 ************************************************************************/
372long int fixed_sdram (void)
373{
374#ifndef CFG_RAMBOOT
375 volatile immap_t *immap = (immap_t *) CFG_IMMR;
376 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
377
378 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
379 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
380 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
381 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
382 ddr->sdram_mode = CFG_DDR_MODE;
383 ddr->sdram_interval = CFG_DDR_INTERVAL;
384 ddr->err_disable = 0x0000000D;
385#if defined (CONFIG_DDR_ECC)
386 ddr->err_disable = 0x0000000D;
387 ddr->err_sbe = 0x00ff0000;
388#endif
389 asm ("sync;isync;msync");
390 udelay (500);
391#if defined (CONFIG_DDR_ECC)
392 /* Enable ECC checking */
393 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
394#else
395 ddr->sdram_cfg = CFG_DDR_CONTROL;
396#endif
397 asm ("sync; isync; msync");
398 udelay (500);
399#endif
400 return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
401}
402#endif /* !defined(CONFIG_SPD_EEPROM) */
403
404
405#if defined(CONFIG_PCI)
406/*
407 * Initialize PCI Devices, report devices found.
408 */
409
410#ifndef CONFIG_PCI_PNP
411static struct pci_config_table pci_mpc85xxads_config_table[] = {
412 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
413 PCI_IDSEL_NUMBER, PCI_ANY_ID,
414 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
415 PCI_ENET0_MEMADDR,
416 PCI_COMMAND_MEMORY |
417 PCI_COMMAND_MASTER}},
418 {}
419};
420#endif
421
422
423static struct pci_controller hose = {
424#ifndef CONFIG_PCI_PNP
425 config_table:pci_mpc85xxads_config_table,
426#endif
427};
428
429#endif /* CONFIG_PCI */
430
431
432void pci_init_board (void)
433{
434#ifdef CONFIG_PCI
435 extern void pci_mpc85xx_init (struct pci_controller *hose);
436
437 pci_mpc85xx_init (&hose);
438#endif /* CONFIG_PCI */
439}