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Chunhe Lan57072332013-06-14 16:21:48 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <Chunhe.Lan@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Chunhe Lan57072332013-06-14 16:21:48 +08008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Chunhe Lanfb735722014-11-07 15:15:49 +080013#define CONFIG_SYS_GENERIC_BOARD
14#define CONFIG_DISPLAY_BOARDINFO
15
Chunhe Lan57072332013-06-14 16:21:48 +080016#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053017#define CONFIG_SYS_TEXT_BASE 0xeff40000
Chunhe Lan57072332013-06-14 16:21:48 +080018#endif
19
20#ifndef CONFIG_SYS_MONITOR_BASE
21#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
22#endif
23
24#ifndef CONFIG_RESET_VECTOR_ADDRESS
25#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
26#endif
27
28/* High Level Configuration Options */
29#define CONFIG_BOOKE /* BOOKE */
30#define CONFIG_E500 /* BOOKE e500 family */
Chunhe Lan57072332013-06-14 16:21:48 +080031#define CONFIG_P1023
32#define CONFIG_MP /* support multiple processors */
33
34#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
35#define CONFIG_PCI /* Enable PCI/PCIE */
36#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
37#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
38#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
39#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
40#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
41#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
42#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
43#define CONFIG_FSL_LAW /* Use common FSL init code */
44
45#ifndef __ASSEMBLY__
46extern unsigned long get_clock_freq(void);
47#endif
48
49#define CONFIG_SYS_CLK_FREQ 66666666
50#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
51
52/*
53 * These can be toggled for performance analysis, otherwise use default.
54 */
55#define CONFIG_L2_CACHE /* toggle L2 cache */
56#define CONFIG_BTB /* toggle branch predition */
57#define CONFIG_HWCONFIG
58
59#define CONFIG_ENABLE_36BIT_PHYS
60
61#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
62#define CONFIG_SYS_MEMTEST_END 0x02000000
63
64#define CONFIG_PANIC_HANG /* do not reset board on panic */
65
66/* Implement conversion of addresses in the LBC */
67#define CONFIG_SYS_LBC_LBCR 0x00000000
68#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
69
70/* DDR Setup */
71#define CONFIG_VERY_BIG_RAM
72#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
73#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
74
75#define CONFIG_DIMM_SLOTS_PER_CTLR 1
76#define CONFIG_CHIP_SELECTS_PER_CTRL 1
77
78#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -070079#define CONFIG_SYS_FSL_DDR3
Chunhe Lan57072332013-06-14 16:21:48 +080080#define CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
82#define CONFIG_SYS_SPD_BUS_NUM 0
83#define SPD_EEPROM_ADDRESS 0x50
84#define CONFIG_SYS_DDR_RAW_TIMING
85
86/*
87 * Memory map
88 *
89 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
90 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
91 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
92 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
93 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
94 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
95 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
96 *
97 * Localbus non-cacheable
98 *
99 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
100 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
101 */
102
103/*
104 * Local Bus Definitions
105 */
106#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
107#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
108
109#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
110 | BR_PS_16 | BR_V)
111#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
112
113#define CONFIG_FLASH_CFI_DRIVER
114#define CONFIG_SYS_FLASH_CFI
115#define CONFIG_SYS_FLASH_EMPTY_INFO
116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
118#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
119#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
120
121#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
122#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
123
124#define CONFIG_SYS_INIT_RAM_LOCK
125#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
126#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
127#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
128 GENERATED_GBL_DATA_SIZE)
129#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
130
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530131#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
Chunhe Lan57072332013-06-14 16:21:48 +0800132#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
133
134#define CONFIG_SYS_NAND_BASE 0xffa00000
135#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
136
137#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
138#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan57072332013-06-14 16:21:48 +0800139#define CONFIG_CMD_NAND
140#define CONFIG_NAND_FSL_ELBC
141#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
142
143/* NAND flash config */
144#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
145 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
146 | BR_PS_8 /* Port Size = 8bit */ \
147 | BR_MS_FCM /* MSEL = FCM */ \
148 | BR_V) /* valid */
149#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
150 | OR_FCM_PGS \
151 | OR_FCM_CSCT \
152 | OR_FCM_CST \
153 | OR_FCM_CHT \
154 | OR_FCM_SCY_1 \
155 | OR_FCM_TRLX \
156 | OR_FCM_EHTR)
157
158#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
159#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
160#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
161#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
162
163/* Serial Port */
164#define CONFIG_CONS_INDEX 1
165#undef CONFIG_SERIAL_SOFTWARE_FIFO
166#define CONFIG_SYS_NS16550
167#define CONFIG_SYS_NS16550_SERIAL
168#define CONFIG_SYS_NS16550_REG_SIZE 1
169#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
170
171#define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
173
174#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
175#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
176
177/* Use the HUSH parser */
178#define CONFIG_SYS_HUSH_PARSER
179
180/*
181 * Pass open firmware flat tree
182 */
183#define CONFIG_OF_LIBFDT
184#define CONFIG_OF_BOARD_SETUP
185#define CONFIG_OF_STDOUT_VIA_ALIAS
186
187/* new uImage format support */
188#define CONFIG_FIT
189#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
190
191/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200192#define CONFIG_SYS_I2C
193#define CONFIG_SYS_I2C_FSL
194#define CONFIG_SYS_FSL_I2C_SPEED 400000
195#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
196#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
197#define CONFIG_SYS_FSL_I2C2_SPEED 400000
198#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
199#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Chunhe Lan57072332013-06-14 16:21:48 +0800200
201/*
202 * I2C2 EEPROM
203 */
204#define CONFIG_ID_EEPROM
205#ifdef CONFIG_ID_EEPROM
206#define CONFIG_SYS_I2C_EEPROM_NXID
207#endif
208#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
209#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
210#define CONFIG_SYS_EEPROM_BUS_NUM 0
211
212#define CONFIG_CMD_I2C
213
214/*
215 * General PCI
216 * Memory space is mapped 1-1, but I/O space must start from 0.
217 */
218
219/* controller 3, Slot 1, tgtid 3, Base address b000 */
220#define CONFIG_SYS_PCIE3_NAME "Slot 3"
221#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
222#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
223#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
224#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
225#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
226#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
227#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
228#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
229
230/* controller 2, direct to uli, tgtid 2, Base address 9000 */
231#define CONFIG_SYS_PCIE2_NAME "Slot 2"
232#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
233#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
234#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
235#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
236#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
237#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
238#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
239#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
240
241/* controller 1, Slot 2, tgtid 1, Base address a000 */
242#define CONFIG_SYS_PCIE1_NAME "Slot 1"
243#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
244#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
245#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
246#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
247#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
248#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
249#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
250#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
251
252#if defined(CONFIG_PCI)
253#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
254#define CONFIG_PCI_PNP /* do pci plug-and-play */
255#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
256#endif /* CONFIG_PCI */
257
258/*
259 * Environment
260 */
261#define CONFIG_ENV_OVERWRITE
262
263#define CONFIG_ENV_IS_IN_FLASH
Chunhe Lan57072332013-06-14 16:21:48 +0800264#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Chunhe Lan57072332013-06-14 16:21:48 +0800265#define CONFIG_ENV_SIZE 0x2000
266#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
267
268#define CONFIG_LOADS_ECHO /* echo on for serial download */
269#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
270
271/*
272 * Command line configuration.
273 */
Chunhe Lan57072332013-06-14 16:21:48 +0800274#define CONFIG_CMD_IRQ
275#define CONFIG_CMD_PING
276#define CONFIG_CMD_MII
Chunhe Lan57072332013-06-14 16:21:48 +0800277#define CONFIG_CMD_REGINFO
278
279#if defined(CONFIG_PCI)
280#define CONFIG_CMD_PCI
Chunhe Lan57072332013-06-14 16:21:48 +0800281#endif
282
283/*
284 * USB
285 */
286#define CONFIG_HAS_FSL_DR_USB
287#ifdef CONFIG_HAS_FSL_DR_USB
288#define CONFIG_USB_EHCI
289
290#ifdef CONFIG_USB_EHCI
291#define CONFIG_CMD_USB
292#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
293#define CONFIG_USB_EHCI_FSL
294#define CONFIG_USB_STORAGE
295#define CONFIG_CMD_FAT
296#define CONFIG_CMD_EXT2
297#define CONFIG_CMD_FAT
298#define CONFIG_DOS_PARTITION
299#endif
300#endif
301
302/*
303 * Miscellaneous configurable options
304 */
305#define CONFIG_SYS_LONGHELP /* undef to save memory */
306#define CONFIG_CMDLINE_EDITING /* Command-line editing */
307#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Chunhe Lan57072332013-06-14 16:21:48 +0800308#if defined(CONFIG_CMD_KGDB)
309#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
310#else
311#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
312#endif
313/* Print Buffer Size */
314#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
315#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
316/* Boot Argument Buffer Size */
317#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Chunhe Lan57072332013-06-14 16:21:48 +0800318
319/*
320 * For booting Linux, the board info and command line data
321 * have to be in the first 64 MB of memory, since this is
322 * the maximum mapped by the Linux kernel during initialization.
323 */
324#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
325#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
326
327/*
328 * Environment Configuration
329 */
330#define CONFIG_BOOTFILE "uImage"
331#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
332
333/* default location for tftp and bootm */
334#define CONFIG_LOADADDR 1000000
335
336#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
337
338#define CONFIG_BAUDRATE 115200
339
340/* Qman/Bman */
341#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
342#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
343#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
344#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500345#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
346#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
347#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
348#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
349#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
350 CONFIG_SYS_QMAN_CENA_SIZE)
351#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
352#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800353#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
354#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
355#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500356#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
357#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
358#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
359#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
360#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
361 CONFIG_SYS_BMAN_CENA_SIZE)
362#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
363#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800364
365/* For FM */
366#define CONFIG_SYS_DPAA_FMAN
367#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
368
369#ifdef CONFIG_SYS_DPAA_FMAN
370#define CONFIG_FMAN_ENET
371#define CONFIG_PHY_ATHEROS
372#endif
373
374/* Default address of microcode for the Linux Fman driver */
375/* QE microcode/firmware address */
376#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800377#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Chunhe Lan57072332013-06-14 16:21:48 +0800378#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
379#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
380
381#ifdef CONFIG_FMAN_ENET
382#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
383#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
384
385#define CONFIG_SYS_TBIPA_VALUE 8
386#define CONFIG_MII /* MII PHY management */
387#define CONFIG_ETHPRIME "FM1@DTSEC1"
388#endif
389
390#define CONFIG_EXTRA_ENV_SETTINGS \
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800391 "netdev=eth0\0" \
392 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
393 "loadaddr=1000000\0" \
394 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
395 "tftpflash=tftpboot $loadaddr $uboot; " \
396 "protect off $ubootaddr +$filesize; " \
397 "erase $ubootaddr +$filesize; " \
398 "cp.b $loadaddr $ubootaddr $filesize; " \
399 "protect on $ubootaddr +$filesize; " \
400 "cmp.b $loadaddr $ubootaddr $filesize\0" \
401 "consoledev=ttyS0\0" \
402 "ramdiskaddr=2000000\0" \
403 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
404 "fdtaddr=c00000\0" \
405 "fdtfile=p1023rdb.dtb\0" \
406 "othbootargs=ramdisk_size=600000\0" \
407 "bdev=sda1\0" \
Chunhe Lan57072332013-06-14 16:21:48 +0800408 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
409
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800410#define CONFIG_HDBOOT \
411 "setenv bootargs root=/dev/$bdev rw " \
412 "console=$consoledev,$baudrate $othbootargs;" \
413 "tftp $loadaddr $bootfile;" \
414 "tftp $fdtaddr $fdtfile;" \
415 "bootm $loadaddr - $fdtaddr"
416
417#define CONFIG_NFSBOOTCOMMAND \
418 "setenv bootargs root=/dev/nfs rw " \
419 "nfsroot=$serverip:$rootpath " \
420 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
421 "console=$consoledev,$baudrate $othbootargs;" \
422 "tftp $loadaddr $bootfile;" \
423 "tftp $fdtaddr $fdtfile;" \
424 "bootm $loadaddr - $fdtaddr"
425
426#define CONFIG_RAMBOOTCOMMAND \
427 "setenv bootargs root=/dev/ram rw " \
428 "console=$consoledev,$baudrate $othbootargs;" \
429 "tftp $ramdiskaddr $ramdiskfile;" \
430 "tftp $loadaddr $bootfile;" \
431 "tftp $fdtaddr $fdtfile;" \
432 "bootm $loadaddr $ramdiskaddr $fdtaddr"
433
434#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
435
Chunhe Lan57072332013-06-14 16:21:48 +0800436#endif /* __CONFIG_H */