blob: d0d2eedb6d7cc36e197e003967ed2eace543bdda [file] [log] [blame]
York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_SIMU_H
8#define __LS2_SIMU_H
9
10#include "ls2085a_common.h"
11
Bhupesh Sharmabbeeb8b2015-01-06 13:18:58 -080012#define CONFIG_IDENT_STRING " LS2085A-SIMU"
13#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
14
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070015#define CONFIG_SYS_CLK_FREQ 100000000
16#define CONFIG_DDR_CLK_FREQ 133333333
17
18#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
19#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
20
21#define CONFIG_DIMM_SLOTS_PER_CTLR 1
22#define CONFIG_CHIP_SELECTS_PER_CTRL 4
23#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
24
York Sunf749db32014-06-23 15:15:56 -070025/* SMSC 91C111 ethernet configuration */
26#define CONFIG_SMC91111
27#define CONFIG_SMC91111_BASE (0x2210000)
28
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070029#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
30#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
31
32/*
33 * NOR Flash Timing Params
34 */
35#define CONFIG_SYS_NOR0_CSPR \
36 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
37 CSPR_PORT_SIZE_16 | \
38 CSPR_MSEL_NOR | \
39 CSPR_V)
40#define CONFIG_SYS_NOR0_CSPR_EARLY \
41 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
42 CSPR_PORT_SIZE_16 | \
43 CSPR_MSEL_NOR | \
44 CSPR_V)
45#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
46#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
47 FTIM0_NOR_TEADC(0x1) | \
48 FTIM0_NOR_TEAHC(0x1))
49#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
50 FTIM1_NOR_TRAD_NOR(0x1))
51#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
52 FTIM2_NOR_TCH(0x0) | \
53 FTIM2_NOR_TWP(0x1))
54#define CONFIG_SYS_NOR_FTIM3 0x04000000
55#define CONFIG_SYS_IFC_CCR 0x01000000
56
57#ifndef CONFIG_SYS_NO_FLASH
58#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
59
60#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
61#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
62#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
63#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
64
65#define CONFIG_SYS_FLASH_EMPTY_INFO
66#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
67#endif
68
69#define CONFIG_NAND_FSL_IFC
70#define CONFIG_SYS_NAND_MAX_ECCPOS 256
71#define CONFIG_SYS_NAND_MAX_OOBFREE 2
72
73
74#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
75#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
76 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
77 | CSPR_MSEL_NAND /* MSEL = NAND */ \
78 | CSPR_V)
79#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
80
81#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
82 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
83 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
84 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
85 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
86 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
87 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
88
89#define CONFIG_SYS_NAND_ONFI_DETECTION
90
91/* ONFI NAND Flash mode0 Timing Params */
92#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
93 FTIM0_NAND_TWP(0x18) | \
94 FTIM0_NAND_TWCHT(0x07) | \
95 FTIM0_NAND_TWH(0x0a))
96#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
97 FTIM1_NAND_TWBE(0x39) | \
98 FTIM1_NAND_TRR(0x0e) | \
99 FTIM1_NAND_TRP(0x18))
100#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
101 FTIM2_NAND_TREH(0x0a) | \
102 FTIM2_NAND_TWHRE(0x1e))
103#define CONFIG_SYS_NAND_FTIM3 0x0
104
105#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
106#define CONFIG_SYS_MAX_NAND_DEVICE 1
107#define CONFIG_MTD_NAND_VERIFY_WRITE
108#define CONFIG_CMD_NAND
109
110#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
111
112#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
113#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
114#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
115#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
116#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
117#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
118#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
119#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
120#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530121#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
122#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
123#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
124#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
125#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
126#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
127#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
128#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
129
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700130/* Debug Server firmware */
131#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
132#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
133
134/* MC firmware */
135#define CONFIG_SYS_LS_MC_FW_IN_NOR
136#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
137
138#define CONFIG_SYS_LS_MC_DPL_IN_NOR
139#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
140
J. German Rivera125e2bc2015-03-20 19:28:18 -0700141#define CONFIG_SYS_LS_MC_DPC_IN_NOR
142#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
143
144#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
145
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700146/* Store environment at top of flash */
147#define CONFIG_ENV_IS_NOWHERE 1
148#define CONFIG_ENV_SIZE 0x1000
149
York Sunf749db32014-06-23 15:15:56 -0700150#endif /* __LS2_SIMU_H */