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Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_AVR32 1
28#define CONFIG_AT32AP 1
29#define CONFIG_AT32AP7000 1
30#define CONFIG_ATSTK1002 1
31#define CONFIG_ATSTK1000 1
32
33#define CONFIG_ATSTK1000_EXT_FLASH 1
34
35/*
36 * Timer clock frequency. We're using the CPU-internal COUNT register
37 * for this, so this is equivalent to the CPU core clock frequency
38 */
39#define CFG_HZ 1000
40
41/*
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020042 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
43 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
44 * PLL frequency.
45 * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
Wolfgang Denk6ccec442006-10-24 14:42:37 +020046 */
47#define CONFIG_PLL 1
48#define CFG_POWER_MANAGER 1
49#define CFG_OSC0_HZ 20000000
50#define CFG_PLL0_DIV 1
51#define CFG_PLL0_MUL 7
52#define CFG_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020053/*
54 * Set the CPU running at:
55 * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
56 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020057#define CFG_CLKDIV_CPU 0
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020058/*
59 * Set the HSB running at:
60 * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
61 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020062#define CFG_CLKDIV_HSB 1
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020063/*
64 * Set the PBA running at:
65 * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
66 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020067#define CFG_CLKDIV_PBA 2
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020068/*
69 * Set the PBB running at:
70 * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
71 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020072#define CFG_CLKDIV_PBB 1
73
74/*
75 * The PLLOPT register controls the PLL like this:
76 * icp = PLLOPT<2>
77 * ivco = PLLOPT<1:0>
78 *
79 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
80 */
81#define CFG_PLL0_OPT 0x04
82
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010083#undef CONFIG_USART0
84#define CONFIG_USART1 1
85#undef CONFIG_USART2
86#undef CONFIG_USART3
Wolfgang Denk6ccec442006-10-24 14:42:37 +020087
88/* User serviceable stuff */
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010089#define CONFIG_DOS_PARTITION 1
90
Wolfgang Denk6ccec442006-10-24 14:42:37 +020091#define CONFIG_CMDLINE_TAG 1
92#define CONFIG_SETUP_MEMORY_TAGS 1
93#define CONFIG_INITRD_TAG 1
94
95#define CONFIG_STACKSIZE (2048)
96
97#define CONFIG_BAUDRATE 115200
98#define CONFIG_BOOTARGS \
Eirik Aanonsene80e5852007-09-18 08:47:20 +020099 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100100
101#define CONFIG_BOOTCOMMAND \
102 "fsload; bootm $(fileaddr)"
103
104/*
105 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
106 * data on the serial line may interrupt the boot sequence.
107 */
Hans-Christian Egtvedt696dd132007-08-30 15:03:05 +0200108#define CONFIG_BOOTDELAY 1
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100109#define CONFIG_AUTOBOOT 1
110#define CONFIG_AUTOBOOT_KEYED 1
111#define CONFIG_AUTOBOOT_PROMPT \
Wolfgang Denkb99c1e62007-04-18 16:53:52 +0200112 "Press SPACE to abort autoboot in %d seconds\n"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100113#define CONFIG_AUTOBOOT_DELAY_STR "d"
114#define CONFIG_AUTOBOOT_STOP_STR " "
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200115
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100116/*
Haavard Skinnemoen8b6684a2007-10-24 15:48:37 +0200117 * After booting the board for the first time, new ethernet addresses
118 * should be generated and assigned to the environment variables
119 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100120 */
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100121#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
122#define CONFIG_NET_MULTI 1
123
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500124/*
125 * BOOTP options
126 */
127#define CONFIG_BOOTP_SUBNETMASK
128#define CONFIG_BOOTP_GATEWAY
129
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200130
Jon Loeliger0b361c92007-07-04 22:31:42 -0500131/*
132 * Command line configuration.
133 */
134#include <config_cmd_default.h>
135
136#define CONFIG_CMD_ASKENV
137#define CONFIG_CMD_DHCP
138#define CONFIG_CMD_EXT2
139#define CONFIG_CMD_FAT
140#define CONFIG_CMD_JFFS2
141#define CONFIG_CMD_MMC
142#define CONFIG_CMD_REGINFO
143
144#undef CONFIG_CMD_AUTOSCRIPT
145#undef CONFIG_CMD_SETGETDCR
146#undef CONFIG_CMD_XIMG
147
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200148#define CONFIG_ATMEL_USART 1
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100149#define CONFIG_MACB 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200150#define CONFIG_PIO2 1
151#define CFG_NR_PIOS 5
152#define CFG_HSDRAMC 1
Haavard Skinnemoen8e687512006-12-17 18:56:46 +0100153#define CONFIG_MMC 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200154
155#define CFG_DCACHE_LINESZ 32
156#define CFG_ICACHE_LINESZ 32
157
158#define CONFIG_NR_DRAM_BANKS 1
159
160/* External flash on STK1000 */
161#if 0
162#define CFG_FLASH_CFI 1
163#define CFG_FLASH_CFI_DRIVER 1
164#endif
165
166#define CFG_FLASH_BASE 0x00000000
167#define CFG_FLASH_SIZE 0x800000
168#define CFG_MAX_FLASH_BANKS 1
169#define CFG_MAX_FLASH_SECT 135
170
171#define CFG_MONITOR_BASE CFG_FLASH_BASE
172
173#define CFG_INTRAM_BASE 0x24000000
174#define CFG_INTRAM_SIZE 0x8000
175
176#define CFG_SDRAM_BASE 0x10000000
177
178#define CFG_ENV_IS_IN_FLASH 1
179#define CFG_ENV_SIZE 65536
180#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
181
182#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
183
184#define CFG_MALLOC_LEN (256*1024)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200185#define CFG_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen1f4f2122006-11-20 15:53:10 +0100186
Haavard Skinnemoen8269ab52007-11-22 17:01:24 +0100187/* Allow 4MB for the kernel run-time image */
188#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200189#define CFG_BOOTPARAMS_LEN (16 * 1024)
190
191/* Other configuration settings that shouldn't have to change all that often */
192#define CFG_PROMPT "Uboot> "
193#define CFG_CBSIZE 256
194#define CFG_MAXARGS 8
195#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
196#define CFG_LONGHELP 1
197
Haavard Skinnemoen9add9882007-10-02 19:09:01 +0200198#define CFG_MEMTEST_START CFG_SDRAM_BASE
199#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200200#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
201
202#endif /* __CONFIG_H */