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Stefan Roese6983fe22008-03-11 16:52:24 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/************************************************************************
22 * canyonlands.h - configuration for Canyonlands (460EX)
23 ***********************************************************************/
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
Stefan Roese4c9e8552008-03-19 16:20:49 +010030/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
31#ifndef CONFIG_CANYONLANDS
32#define CONFIG_460GT 1 /* Specific PPC460GT */
33#else
34#define CONFIG_460EX 1 /* Specific PPC460EX */
35#endif
Stefan Roese6983fe22008-03-11 16:52:24 +010036#define CONFIG_440 1
37#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese6983fe22008-03-11 16:52:24 +010038
39#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
43#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roesecc8e8392008-03-28 14:09:04 +010044#define CONFIG_BOARD_TYPES 1 /* support board types */
Stefan Roese6983fe22008-03-11 16:52:24 +010045
46/*-----------------------------------------------------------------------
47 * Base addresses -- Note these are effective addresses where the
48 * actual resources get mapped (not physical addresses)
49 *----------------------------------------------------------------------*/
50#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
51
52#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
53#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
54#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
55
56#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
57#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
58#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
59
60#define CFG_PCIE0_CFGBASE 0xc0000000
61#define CFG_PCIE1_CFGBASE 0xc1000000
62#define CFG_PCIE0_XCFGBASE 0xc3000000
63#define CFG_PCIE1_XCFGBASE 0xc3001000
64
65#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
66
67/* base address of inbound PCIe window */
68#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
69
70/* EBC stuff */
71#define CFG_NAND_ADDR 0xE0000000
72#define CFG_BCSR_BASE 0xE1000000
73#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
74#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
75#define CFG_FLASH_BASE_PHYS_H 0x4
76#define CFG_FLASH_BASE_PHYS_L 0xCC000000
77#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
78 (u64)CFG_FLASH_BASE_PHYS_L)
79#define CFG_FLASH_SIZE (64 << 20)
80
81#define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
82#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
83#define CFG_LOCAL_CONF_REGS 0xEF000000
84
85#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
86
Stefan Roese41712b42008-03-05 12:31:53 +010087#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
88
Stefan Roese6983fe22008-03-11 16:52:24 +010089#define CFG_MONITOR_BASE TEXT_BASE
90#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
91#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
92
93/*-----------------------------------------------------------------------
94 * Initial RAM & stack pointer (placed in OCM)
95 *----------------------------------------------------------------------*/
96#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
97#define CFG_INIT_RAM_END (4 << 10)
98#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
99#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
100#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
101
102/*-----------------------------------------------------------------------
103 * Serial Port
104 *----------------------------------------------------------------------*/
105#define CONFIG_BAUDRATE 115200
106#define CONFIG_SERIAL_MULTI 1
107#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
108
109#define CFG_BAUDRATE_TABLE \
110 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
111
112/*-----------------------------------------------------------------------
113 * Environment
114 *----------------------------------------------------------------------*/
115/*
116 * Define here the location of the environment variables (FLASH).
117 */
118#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
119#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
120#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
121#else
122#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
123#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
Stefan Roese71665eb2008-03-03 17:27:02 +0100124#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
125#endif
126
127/*
128 * IPL (Initial Program Loader, integrated inside CPU)
129 * Will load first 4k from NAND (SPL) into cache and execute it from there.
130 *
131 * SPL (Secondary Program Loader)
132 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
133 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
134 * controller and the NAND controller so that the special U-Boot image can be
135 * loaded from NAND to SDRAM.
136 *
137 * NUB (NAND U-Boot)
138 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
139 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
140 *
141 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
142 * set up. While still running from cache, I experienced problems accessing
143 * the NAND controller. sr - 2006-08-25
144 */
145#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
146#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
147#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
148#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
149#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
150 /* this addr */
151#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
152
153/*
154 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
155 */
156#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
157#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
158
159/*
160 * Now the NAND chip has to be defined (no autodetection used!)
161 */
162#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
163#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
164#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
165#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
166#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
167
168#define CFG_NAND_ECCSIZE 256
169#define CFG_NAND_ECCBYTES 3
170#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
171#define CFG_NAND_OOBSIZE 16
172#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
173#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
174
175#ifdef CFG_ENV_IS_IN_NAND
176/*
177 * For NAND booting the environment is embedded in the U-Boot image. Please take
178 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
179 */
180#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
181#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
182#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
Stefan Roese6983fe22008-03-11 16:52:24 +0100183#endif
184
185/*-----------------------------------------------------------------------
186 * FLASH related
187 *----------------------------------------------------------------------*/
188#define CFG_FLASH_CFI /* The flash is CFI compatible */
189#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
190#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
191
192#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
193#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
194#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
195
196#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
197#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
198
199#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
200#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
201
202#ifdef CFG_ENV_IS_IN_FLASH
203#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
204#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
205#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
206
207/* Address and size of Redundant Environment Sector */
208#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
209#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
210#endif /* CFG_ENV_IS_IN_FLASH */
211
212/*-----------------------------------------------------------------------
213 * NAND-FLASH related
214 *----------------------------------------------------------------------*/
215#define CFG_MAX_NAND_DEVICE 1
216#define NAND_MAX_CHIPS 1
217#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
218#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
219
220/*------------------------------------------------------------------------------
221 * DDR SDRAM
222 *----------------------------------------------------------------------------*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100223#if !defined(CONFIG_NAND_U_BOOT)
224/*
225 * NAND booting U-Boot version uses a fixed initialization, since the whole
226 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
227 * code.
228 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100229#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
230#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
231#define CONFIG_DDR_ECC 1 /* with ECC support */
232#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
Stefan Roese71665eb2008-03-03 17:27:02 +0100233#endif
234#define CFG_MBYTES_SDRAM 256 /* 256MB */
Stefan Roese6983fe22008-03-11 16:52:24 +0100235
236/*-----------------------------------------------------------------------
237 * I2C
238 *----------------------------------------------------------------------*/
239#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
240#undef CONFIG_SOFT_I2C /* I2C bit-banged */
241#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
242#define CFG_I2C_SLAVE 0x7F
243
244#define CFG_I2C_MULTI_EEPROMS
245#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
246#define CFG_I2C_EEPROM_ADDR_LEN 1
247#define CFG_EEPROM_PAGE_WRITE_ENABLE
248#define CFG_EEPROM_PAGE_WRITE_BITS 3
249#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
250
251/* I2C SYSMON (LM75, AD7414 is almost compatible) */
252#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
253#define CONFIG_DTT_AD7414 1 /* use AD7414 */
254#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
255#define CFG_DTT_MAX_TEMP 70
256#define CFG_DTT_LOW_TEMP -30
257#define CFG_DTT_HYSTERESIS 3
258
259/* RTC configuration */
260#define CONFIG_RTC_M41T62 1
261#define CFG_I2C_RTC_ADDR 0x68
262
263/*-----------------------------------------------------------------------
264 * Ethernet
265 *----------------------------------------------------------------------*/
266#define CONFIG_IBM_EMAC4_V4 1
267#define CONFIG_MII 1 /* MII PHY management */
268#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
269#define CONFIG_PHY1_ADDR 1
Stefan Roese4c9e8552008-03-19 16:20:49 +0100270#define CONFIG_HAS_ETH0
271#define CONFIG_HAS_ETH1
272/* Only Glacier (460GT) has 4 EMAC interfaces */
273#ifdef CONFIG_460GT
274#define CONFIG_PHY2_ADDR 2
275#define CONFIG_PHY3_ADDR 3
276#define CONFIG_HAS_ETH2
277#define CONFIG_HAS_ETH3
278#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100279#define CONFIG_NET_MULTI 1
280
281#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
282#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
283#define CONFIG_PHY_DYNAMIC_ANEG 1
284
285#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
286
Stefan Roese41712b42008-03-05 12:31:53 +0100287/*-----------------------------------------------------------------------
288 * USB-OHCI
289 *----------------------------------------------------------------------*/
Stefan Roese4c9e8552008-03-19 16:20:49 +0100290/* Only Canyonlands (460EX) has USB */
291#ifdef CONFIG_460EX
Stefan Roese41712b42008-03-05 12:31:53 +0100292#define CONFIG_USB_OHCI_NEW
293#define CONFIG_USB_STORAGE
294#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
295#define CFG_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
296#define CFG_OHCI_USE_NPS /* force NoPowerSwitching mode */
297#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
298#define CFG_USB_OHCI_SLOT_NAME "ppc440"
299#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
Stefan Roese4c9e8552008-03-19 16:20:49 +0100300#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100301
302/*-----------------------------------------------------------------------
303 * Default environment
304 *----------------------------------------------------------------------*/
Stefan Roese6983fe22008-03-11 16:52:24 +0100305#define CONFIG_PREBOOT "echo;" \
306 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
307 "echo"
308
309#undef CONFIG_BOOTARGS
310
Stefan Roese4c9e8552008-03-19 16:20:49 +0100311/* Setup some board specific values for the default environment variables */
312#ifdef CONFIG_CANYONLANDS
313#define CONFIG_HOSTNAME canyonlands
314#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
315#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
316#else
317#define CONFIG_HOSTNAME glacier
318#define CFG_BOOTFILE "bootfile=glacier/uImage\0"
319#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
320#endif
321
Stefan Roese6983fe22008-03-11 16:52:24 +0100322#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100323 CFG_BOOTFILE \
324 CFG_DTBFILE \
Stefan Roese6983fe22008-03-11 16:52:24 +0100325 "netdev=eth0\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100326 "nfsargs=setenv bootargs root=/dev/nfs rw " \
327 "nfsroot=${serverip}:${rootpath}\0" \
328 "ramargs=setenv bootargs root=/dev/ram rw\0" \
329 "addip=setenv bootargs ${bootargs} " \
330 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
331 ":${hostname}:${netdev}:off panic=1\0" \
332 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese756f5da2008-04-09 11:58:02 +0200333 "net_nfs=tftp 400000 ${bootfile};" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100334 "tftp ${fdt_addr} ${fdt_file};" \
335 "run nfsargs addip addtty;" \
Stefan Roese756f5da2008-04-09 11:58:02 +0200336 "bootm 400000 - ${fdt_addr}\0" \
337 "net_nfs_fdt=net_nfs\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100338 "flash_nfs=run nfsargs addip addtty;" \
339 "bootm ${kernel_addr}\0" \
340 "flash_self=run ramargs addip addtty;" \
341 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
342 "rootpath=/opt/eldk/ppc_4xxFP\0" \
Stefan Roese756f5da2008-04-09 11:58:02 +0200343 "fdt_addr=800000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100344 "kernel_addr=fc000000\0" \
345 "ramdisk_addr=fc200000\0" \
346 "initrd_high=30000000\0" \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100347 "load=tftp 200000 ${hostname}/u-boot.bin\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100348 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
349 "cp.b ${fileaddr} fffa0000 ${filesize};" \
350 "setenv filesize;saveenv\0" \
351 "upd=run load update\0" \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100352 "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
Stefan Roese756f5da2008-04-09 11:58:02 +0200353 "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100354 "setenv filesize;saveenv\0" \
355 "nupd=run nload nupdate\0" \
356 "pciconfighost=1\0" \
357 "pcie_mode=RP:RP\0" \
358 ""
359#define CONFIG_BOOTCOMMAND "run flash_self"
360
361#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
362
363#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
364#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
365
366/*
367 * BOOTP options
368 */
369#define CONFIG_BOOTP_BOOTFILESIZE
370#define CONFIG_BOOTP_BOOTPATH
371#define CONFIG_BOOTP_GATEWAY
372#define CONFIG_BOOTP_HOSTNAME
373#define CONFIG_BOOTP_SUBNETMASK
374
375/*
376 * Command line configuration.
377 */
378#include <config_cmd_default.h>
379
380#define CONFIG_CMD_ASKENV
381#define CONFIG_CMD_DATE
382#define CONFIG_CMD_DHCP
383#define CONFIG_CMD_DTT
384#define CONFIG_CMD_DIAG
385#define CONFIG_CMD_EEPROM
386#define CONFIG_CMD_ELF
Stefan Roese6983fe22008-03-11 16:52:24 +0100387#define CONFIG_CMD_I2C
388#define CONFIG_CMD_IRQ
389#define CONFIG_CMD_MII
390#define CONFIG_CMD_NAND
391#define CONFIG_CMD_NET
392#define CONFIG_CMD_NFS
393#define CONFIG_CMD_PCI
394#define CONFIG_CMD_PING
395#define CONFIG_CMD_REGINFO
396#define CONFIG_CMD_SDRAM
Stefan Roese4c9e8552008-03-19 16:20:49 +0100397#ifdef CONFIG_460EX
398#define CONFIG_CMD_EXT2
399#define CONFIG_CMD_FAT
Stefan Roese41712b42008-03-05 12:31:53 +0100400#define CONFIG_CMD_USB
Stefan Roese4c9e8552008-03-19 16:20:49 +0100401#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100402
403/* Partitions */
404#define CONFIG_MAC_PARTITION
405#define CONFIG_DOS_PARTITION
406#define CONFIG_ISO_PARTITION
Stefan Roese6983fe22008-03-11 16:52:24 +0100407
408/*-----------------------------------------------------------------------
409 * Miscellaneous configurable options
410 *----------------------------------------------------------------------*/
411#define CFG_LONGHELP /* undef to save memory */
412#define CFG_PROMPT "=> " /* Monitor Command Prompt */
413#if defined(CONFIG_CMD_KGDB)
414#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
415#else
416#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
417#endif
418#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
419#define CFG_MAXARGS 16 /* max number of command args */
420#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
421
422#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
423#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
424
425#define CFG_LOAD_ADDR 0x100000 /* default load address */
426#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
427
428#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
429
430#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
431#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
432#define CONFIG_LOOPW 1 /* enable loopw command */
433#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
434#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
435#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
436#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
437
438#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
439#ifdef CFG_HUSH_PARSER
440#define CFG_PROMPT_HUSH_PS2 "> "
441#endif
442
443/*-----------------------------------------------------------------------
444 * PCI stuff
445 *----------------------------------------------------------------------*/
446/* General PCI */
447#define CONFIG_PCI /* include pci support */
448#define CONFIG_PCI_PNP /* do pci plug-and-play */
449#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
450#define CONFIG_PCI_CONFIG_HOST_BRIDGE
451
452/* Board-specific PCI */
453#define CFG_PCI_TARGET_INIT /* let board init pci target */
454#undef CFG_PCI_MASTER_INIT
455
456#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
457#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
458
459/*
460 * For booting Linux, the board info and command line data
461 * have to be in the first 8 MB of memory, since this is
462 * the maximum mapped by the Linux kernel during initialization.
463 */
464#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
465
466/*
467 * Internal Definitions
468 */
469#if defined(CONFIG_CMD_KGDB)
470#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
471#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
472#endif
473
474/*-----------------------------------------------------------------------
475 * External Bus Controller (EBC) Setup
476 *----------------------------------------------------------------------*/
477
478/*
479 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
480 * boot EBC mapping only supports a maximum of 16MBytes
481 * (4.ff00.0000 - 4.ffff.ffff).
482 * To solve this problem, the FLASH has to get remapped to another
483 * EBC address which accepts bigger regions:
484 *
485 * 0xfc00.0000 -> 4.cc00.0000
Stefan Roese6983fe22008-03-11 16:52:24 +0100486 */
487
Stefan Roese71665eb2008-03-03 17:27:02 +0100488#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
489/* Memory Bank 3 (NOR-FLASH) initialization */
490#define CFG_EBC_PB3AP 0x10055e00
491#define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000)
492
493/* Memory Bank 0 (NAND-FLASH) initialization */
494#define CFG_EBC_PB0AP 0x018003c0
495#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
496#else
Stefan Roese6983fe22008-03-11 16:52:24 +0100497/* Memory Bank 0 (NOR-FLASH) initialization */
498#define CFG_EBC_PB0AP 0x10055e00
499#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
500
Stefan Roese6983fe22008-03-11 16:52:24 +0100501/* Memory Bank 3 (NAND-FLASH) initialization */
502#define CFG_EBC_PB3AP 0x018003c0
503#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100504#endif
505
506/* Memory Bank 2 (CPLD) initialization */
507#define CFG_EBC_PB2AP 0x00804240
508#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
Stefan Roese6983fe22008-03-11 16:52:24 +0100509
510#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
511
512/*
513 * PPC4xx GPIO Configuration
514 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100515#ifdef CONFIG_460EX
516/* 460EX: Use USB configuration */
Stefan Roese6983fe22008-03-11 16:52:24 +0100517#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
518{ \
519/* GPIO Core 0 */ \
Stefan Roese41712b42008-03-05 12:31:53 +0100520{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
521{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
522{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
523{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
524{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
525{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
526{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
527{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
528{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
529{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
530{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
531{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
532{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
533{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
534{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
535{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
536{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
537{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
538{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
539{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
540{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
541{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
543{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
544{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
545{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
546{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
547{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
548{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
549{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
550{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
551{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
552}, \
553{ \
554/* GPIO Core 1 */ \
555{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
556{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
557{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
558{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
559{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
560{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
561{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
562{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
563{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
564{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
565{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
566{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
567{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
568{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
569{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
570{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
571{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
572{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
573{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
574{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
575{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
577{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
578{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
579{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
580{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
581{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
582{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
583{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
584{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
585{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
586{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
587} \
588}
Stefan Roese4c9e8552008-03-19 16:20:49 +0100589#else
590/* 460GT: Use EMAC2+3 configuration */
591#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
592{ \
593/* GPIO Core 0 */ \
594{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
595{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
596{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
597{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
598{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
599{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
600{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
601{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
602{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
603{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
604{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
605{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
606{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
607{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
608{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
609{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
610{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
611{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
612{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
613{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
614{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
615{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
616{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
617{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
618{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
619{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
620{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
621{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
622{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
623{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
624{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
625{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
626}, \
627{ \
628/* GPIO Core 1 */ \
629{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
630{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
631{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
632{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
633{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
634{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
635{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
636{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
637{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
638{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
639{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
640{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
641{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
642{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
643{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
644{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
645{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
646{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
647{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
648{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
649{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
650{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
651{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
652{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
653{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
654{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
655{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
656{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
657{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
658{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
659{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
660{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
661} \
662}
663#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100664
665/* pass open firmware flat tree */
666#define CONFIG_OF_LIBFDT 1
667#define CONFIG_OF_BOARD_SETUP 1
668
669#endif /* __CONFIG_H */