blob: 7a2863cfd2fe085ec85caacc72472b7de469c97a [file] [log] [blame]
Benoît Thébaudeau112fd2e2013-04-23 10:17:44 +00001Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP)
2on MXC
3
4This IP can be found on the following SoCs:
Alison Wang0454e0c2013-05-27 22:55:46 +00005 - Vybrid VF610,
Benoît Thébaudeau112fd2e2013-04-23 10:17:44 +00006 - i.MX6.
7
8Note that this IP is different from albeit similar to the IPs of the same name
9that can be found on the following SoCs:
10 - i.MX23,
11 - i.MX28,
12 - i.MX50.
13
14The section numbers in this file refer to the i.MX6 Reference Manual.
15
16A fuse word contains 32 fuse bit slots, as explained in 46.2.1.
17
18A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the
19memory map in 46.4.
20
21Some fuse bit or word slots may not have the corresponding fuses actually
22implemented in the fusebox.
23
24See the README files of the SoCs using this driver in order to know the
25conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
26addresses.
27
28Fuse operations:
29
30 Read
31 Read operations are implemented as read accesses to the shadow registers,
32 using "Bankx Wordy" from the memory map in 46.4. This is explained in
33 detail by the first two paragraphs in 46.2.1.2.
34
35 Sense
36 Sense operations are implemented as the direct fusebox read explained by
37 the steps in 46.2.1.2.
38
39 Program
40 Program operations are implemented as explained by the steps in 46.2.1.3.
41 Following this operation, the shadow registers are not reloaded by the
42 hardware.
43
44 Override
45 Override operations are implemented as write accesses to the shadow
46 registers, as explained by the first paragraph in 46.2.1.3.
47
48Configuration:
49
50 CONFIG_MXC_OCOTP
51 Define this to enable the mxc_ocotp driver.