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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenkf12e5682003-07-07 20:07:54 +000041#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020042#define CONFIG_SYS_SMC_RXBUFLEN 128
43#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000044#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000045
wdenkae3af052003-08-07 22:18:11 +000046#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000047
Wolfgang Denke7e00102011-11-04 15:55:51 +000048#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49
wdenkf12e5682003-07-07 20:07:54 +000050#define CONFIG_BOARD_TYPES 1 /* support board types */
51
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf12e5682003-07-07 20:07:54 +000053
54#undef CONFIG_BOOTARGS
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "netdev=eth0\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000060 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000064 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000066 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000069 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020070 "hostname=TQM850M\0" \
71 "bootfile=TQM850M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020072 "fdt_addr=40080000\0" \
73 "kernel_addr=400A0000\0" \
74 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020075 "u-boot=TQM850M/u-image.bin\0" \
76 "load=tftp 200000 ${u-boot}\0" \
77 "update=prot off 40000000 +${filesize};" \
78 "era 40000000 +${filesize};" \
79 "cp.b 200000 40000000 ${filesize};" \
80 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000081 ""
82#define CONFIG_BOOTCOMMAND "run flash_self"
83
84#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000086
87#undef CONFIG_WATCHDOG /* watchdog disabled */
88
89#define CONFIG_STATUS_LED 1 /* Status LED enabled */
90
91#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
92
Jon Loeliger37d4bb72007-07-09 21:38:02 -050093/*
94 * BOOTP options
95 */
96#define CONFIG_BOOTP_SUBNETMASK
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99#define CONFIG_BOOTP_BOOTPATH
100#define CONFIG_BOOTP_BOOTFILESIZE
101
wdenkf12e5682003-07-07 20:07:54 +0000102
103#define CONFIG_MAC_PARTITION
104#define CONFIG_DOS_PARTITION
105
106#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
107
Jon Loeliger26946902007-07-04 22:30:50 -0500108/*
109 * Command line configuration.
110 */
111#include <config_cmd_default.h>
wdenkf12e5682003-07-07 20:07:54 +0000112
Jon Loeliger26946902007-07-04 22:30:50 -0500113#define CONFIG_CMD_ASKENV
114#define CONFIG_CMD_DATE
115#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200116#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100117#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500118#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200119#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500120#define CONFIG_CMD_NFS
121#define CONFIG_CMD_SNTP
122
wdenkf12e5682003-07-07 20:07:54 +0000123
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200124#define CONFIG_NETCONSOLE
125
126
wdenkf12e5682003-07-07 20:07:54 +0000127/*
128 * Miscellaneous configurable options
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LONGHELP /* undef to save memory */
131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf12e5682003-07-07 20:07:54 +0000132
Wolfgang Denk2751a952006-10-28 02:29:14 +0200133#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
135#ifdef CONFIG_SYS_HUSH_PARSER
136#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkf12e5682003-07-07 20:07:54 +0000137#endif
138
Jon Loeliger26946902007-07-04 22:30:50 -0500139#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf12e5682003-07-07 20:07:54 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf12e5682003-07-07 20:07:54 +0000156
157/*
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
161 */
162/*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000166
167/*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200171#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000174
175/*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_SDRAM_BASE 0x00000000
181#define CONFIG_SYS_FLASH_BASE 0x40000000
182#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
184#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000185
186/*
187 * For booting Linux, the board info and command line data
188 * have to be in the first 8 MB of memory, since this is
189 * the maximum mapped by the Linux kernel during initialization.
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000192
193/*-----------------------------------------------------------------------
194 * FLASH organization
195 */
wdenkf12e5682003-07-07 20:07:54 +0000196
Martin Krausee318d9e2007-09-27 11:10:08 +0200197/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200199#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
201#define CONFIG_SYS_FLASH_EMPTY_INFO
202#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
203#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000205
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200206#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
208#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
209#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000210
211/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
213#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200216
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200217#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
218
wdenkf12e5682003-07-07 20:07:54 +0000219/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200220 * Dynamic MTD partition support
221 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100222#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200223#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
224#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200225#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
226
227#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
228 "128k(dtb)," \
229 "1920k(kernel)," \
230 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200231 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200232
233/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000234 * Hardware Information Block
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
237#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
238#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000239
240/*-----------------------------------------------------------------------
241 * Cache Configuration
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500244#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000246#endif
247
248/*-----------------------------------------------------------------------
249 * SYPCR - System Protection Control 11-9
250 * SYPCR can only be written once after reset!
251 *-----------------------------------------------------------------------
252 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
253 */
254#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000256 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
257#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000259#endif
260
261/*-----------------------------------------------------------------------
262 * SIUMCR - SIU Module Configuration 11-6
263 *-----------------------------------------------------------------------
264 * PCMCIA config., multi-function pin tri-state
265 */
266#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000268#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000270#endif /* CONFIG_CAN_DRIVER */
271
272/*-----------------------------------------------------------------------
273 * TBSCR - Time Base Status and Control 11-26
274 *-----------------------------------------------------------------------
275 * Clear Reference Interrupt Status, Timebase freezing enabled
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000278
279/*-----------------------------------------------------------------------
280 * RTCSC - Real-Time Clock Status and Control Register 11-27
281 *-----------------------------------------------------------------------
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000284
285/*-----------------------------------------------------------------------
286 * PISCR - Periodic Interrupt Status and Control 11-31
287 *-----------------------------------------------------------------------
288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000291
292/*-----------------------------------------------------------------------
293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
294 *-----------------------------------------------------------------------
295 * Reset PLL lock status sticky bit, timer expired status bit and timer
296 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000299
300/*-----------------------------------------------------------------------
301 * SCCR - System Clock and reset Control Register 15-27
302 *-----------------------------------------------------------------------
303 * Set clock output, timebase and RTC source and divider,
304 * power management and some other internal clocks
305 */
306#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000308 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
309 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000310
311/*-----------------------------------------------------------------------
312 * PCMCIA stuff
313 *-----------------------------------------------------------------------
314 *
315 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
317#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
318#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
319#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
320#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
321#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
322#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
323#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000324
325/*-----------------------------------------------------------------------
326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
327 *-----------------------------------------------------------------------
328 */
329
330#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
331
332#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
333#undef CONFIG_IDE_LED /* LED for ide not supported */
334#undef CONFIG_IDE_RESET /* reset for ide not supported */
335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
337#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000342
343/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000345
346/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000348
349/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000351
352/*-----------------------------------------------------------------------
353 *
354 *-----------------------------------------------------------------------
355 *
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000358
359/*
360 * Init Memory Controller:
361 *
362 * BR0/1 and OR0/1 (FLASH)
363 */
364
365#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
366#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
367
368/* used to re-map FLASH both when starting from SRAM or FLASH:
369 * restrict access enough to keep SRAM working (if any)
370 * but not too much to meddle with FLASH accesses
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
373#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000374
375/*
376 * FLASH timing:
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000379 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
382#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
383#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
386#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
387#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000388
389/*
390 * BR2/3 and OR2/3 (SDRAM)
391 *
392 */
393#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
394#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
395#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
396
397/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
401#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000402
403#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
405#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000406#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
408#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
409#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
410#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000411 BR_PS_8 | BR_MS_UPMB | BR_V )
412#endif /* CONFIG_CAN_DRIVER */
413
414/*
415 * Memory Periodic Timer Prescaler
416 *
417 * The Divider for PTA (refresh timer) configuration is based on an
418 * example SDRAM configuration (64 MBit, one bank). The adjustment to
419 * the number of chip selects (NCS) and the actually needed refresh
420 * rate is done by setting MPTPR.
421 *
422 * PTA is calculated from
423 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
424 *
425 * gclk CPU clock (not bus clock!)
426 * Trefresh Refresh cycle * 4 (four word bursts used)
427 *
428 * 4096 Rows from SDRAM example configuration
429 * 1000 factor s -> ms
430 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
431 * 4 Number of refresh cycles per period
432 * 64 Refresh cycle in ms per number of rows
433 * --------------------------------------------
434 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
435 *
436 * 50 MHz => 50.000.000 / Divider = 98
437 * 66 Mhz => 66.000.000 / Divider = 129
438 * 80 Mhz => 80.000.000 / Divider = 156
439 */
wdenke9132ea2004-04-24 23:23:30 +0000440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
442#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000443
444/*
445 * For 16 MBit, refresh rates could be 31.3 us
446 * (= 64 ms / 2K = 125 / quad bursts).
447 * For a simpler initialization, 15.6 us is used instead.
448 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
450 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000451 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
453#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000454
455/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
457#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000458
459/*
460 * MAMR settings for SDRAM
461 */
462
463/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
467/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
471
Heiko Schocher7026ead2010-02-09 15:50:27 +0100472/* pass open firmware flat tree */
473#define CONFIG_OF_LIBFDT 1
474#define CONFIG_OF_BOARD_SETUP 1
475#define CONFIG_HWCONFIG 1
476
wdenkf12e5682003-07-07 20:07:54 +0000477#endif /* __CONFIG_H */