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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the R&S Protocol Board board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenke2211742002-11-02 23:30:20 +000041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xff000000
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010043#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044
wdenkc837dcb2004-01-20 23:12:12 +000045#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
46
wdenke2211742002-11-02 23:30:20 +000047/*
48 * select serial console configuration
49 *
50 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
51 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
52 * for SCC).
53 *
54 * if CONFIG_CONS_NONE is defined, then the serial console routines must
55 * defined elsewhere.
56 */
57#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
58#define CONFIG_CONS_ON_SCC /* define if console on SCC */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020059#undef CONFIG_CONS_NONE /* define if console on neither */
wdenke2211742002-11-02 23:30:20 +000060#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
61
62/*
63 * select ethernet configuration
64 *
65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
67 * for FCC)
68 *
69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050070 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000071 */
72#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
73#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
74#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
75#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
76
77#if (CONFIG_ETHER_INDEX == 2)
78
79/*
80 * - Rx-CLK is CLK13
81 * - Tx-CLK is CLK14
82 * - Select bus for bd/buffers (see 28-13)
83 * - Enable Full Duplex in FSMR
84 */
Mike Frysingerd4590da2011-10-17 05:38:58 +000085# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
86# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
88# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000089
90#endif /* CONFIG_ETHER_INDEX */
91
92
93/* allow to overwrite serial and ethaddr */
94#define CONFIG_ENV_OVERWRITE
95
96/* enable I2C */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020097#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
99#define CONFIG_SYS_I2C_SLAVE 0x30
wdenke2211742002-11-02 23:30:20 +0000100
101
102/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
103#define CONFIG_8260_CLKIN 50000000 /* in Hz */
104
105#define CONFIG_BAUDRATE 115200
106
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500107
108/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500109 * BOOTP options
110 */
111#define CONFIG_BOOTP_BOOTFILESIZE
112#define CONFIG_BOOTP_BOOTPATH
113#define CONFIG_BOOTP_GATEWAY
114#define CONFIG_BOOTP_HOSTNAME
115
116
117/*
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
122#undef CONFIG_CMD_KGDB
123
wdenke2211742002-11-02 23:30:20 +0000124
125/* Define this if you want to boot from 0x00000100. If you don't define
126 * this, you will need to program the bootloader to 0xfff00000, and
127 * get the hardware reset config words at 0xfe000000. The simplest
128 * way to do that is to program the bootloader at both addresses.
129 * It is suggested that you just let U-Boot live at 0x00000000.
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_RSD_BOOT_LOW 1
wdenke2211742002-11-02 23:30:20 +0000132
wdenke2211742002-11-02 23:30:20 +0000133#define CONFIG_BOOTDELAY 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200134#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
wdenke2211742002-11-02 23:30:20 +0000135#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
136#define CONFIG_NETMASK 255.255.0.0
137
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500138#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000139#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
140#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
141#endif
142
143/*
144 * Miscellaneous configurable options
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LONGHELP /* undef to save memory */
147#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500148#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000150#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000152#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
154#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
155#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
158#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000163
164 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000166
167/*
168 * Low Level Configuration Settings
169 * (address mappings, register initial values, etc.)
170 * You should know what you are doing if you make changes here.
171 */
172
173/*-----------------------------------------------------------------------
174 * Physical Memory Map
175 */
176#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
177#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
178
179#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
180#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
181
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200182#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
183#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
wdenke2211742002-11-02 23:30:20 +0000184
185/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
186/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
187
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200188#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
189#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
wdenke2211742002-11-02 23:30:20 +0000190
191/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
192/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
193
194#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
195#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
196
197#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
198#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
199
200#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
201
202#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
203#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_IMMR PHYS_IMMR
wdenke2211742002-11-02 23:30:20 +0000206
207/*-----------------------------------------------------------------------
208 * Reset Address
209 *
210 * In order to reset the CPU, U-Boot jumps to a special address which
211 * causes a machine check exception. The default address for this is
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
wdenke2211742002-11-02 23:30:20 +0000213 * testing the monitor in RAM using a JTAG debugger.
214 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
wdenke2211742002-11-02 23:30:20 +0000216 * cause a bus error on your hardware.
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_RESET_ADDRESS 0x20000000
wdenke2211742002-11-02 23:30:20 +0000219
220/*-----------------------------------------------------------------------
221 * Hard Reset Configuration Words
222 */
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#if defined(CONFIG_SYS_RSD_BOOT_LOW)
225# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenke2211742002-11-02 23:30:20 +0000226#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
228#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
wdenke2211742002-11-02 23:30:20 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230/* get the HRCW ISB field from CONFIG_SYS_IMMR */
231#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
232 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
233 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenke2211742002-11-02 23:30:20 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
wdenke2211742002-11-02 23:30:20 +0000236 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 CONFIG_SYS_RSD_HRCW_IMMR |\
wdenk8bde7f72003-06-27 21:31:46 +0000238 HRCW_MMR00 | \
239 HRCW_APPC10 | \
240 HRCW_CS10PC00 | \
241 HRCW_MODCK_H0000 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
wdenke2211742002-11-02 23:30:20 +0000243
244/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_HRCW_SLAVE1 0
246#define CONFIG_SYS_HRCW_SLAVE2 0
247#define CONFIG_SYS_HRCW_SLAVE3 0
248#define CONFIG_SYS_HRCW_SLAVE4 0
249#define CONFIG_SYS_HRCW_SLAVE5 0
250#define CONFIG_SYS_HRCW_SLAVE6 0
251#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000252
253/*-----------------------------------------------------------------------
254 * Definitions for initial stack pointer and data area (in DPRAM)
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200257#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200258#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000260
261/*-----------------------------------------------------------------------
262 * Start addresses for the final memory configuration
263 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
265 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
wdenke2211742002-11-02 23:30:20 +0000266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
268#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
269/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
270#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
271#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
272#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000273#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
275#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000276
277/*
278 * For booting Linux, the board info and command line data
279 * have to be in the first 8 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization.
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000283
284/*-----------------------------------------------------------------------
285 * FLASH and environment organization
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
288#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
291#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000292
293/* turn off NVRAM env feature */
294#undef CONFIG_NVRAM_ENV
295
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200296#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200297#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
298#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000299
300/*-----------------------------------------------------------------------
301 * Cache Configuration
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500304#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000306#endif
307
308/*-----------------------------------------------------------------------
309 * HIDx - Hardware Implementation-dependent Registers 2-11
310 *-----------------------------------------------------------------------
311 * HID0 also contains cache control - initially enable both caches and
312 * invalidate contents, then the final state leaves only the instruction
313 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
314 * but Soft reset does not.
315 *
316 * HID1 has only read-only information - nothing to set.
317 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
319#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
320#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000321
322/*-----------------------------------------------------------------------
323 * RMR - Reset Mode Register
324 *-----------------------------------------------------------------------
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_RMR 0
wdenke2211742002-11-02 23:30:20 +0000327
328/*-----------------------------------------------------------------------
329 * BCR - Bus Configuration 4-25
330 *-----------------------------------------------------------------------
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_BCR 0x100c0000
wdenke2211742002-11-02 23:30:20 +0000333
334/*-----------------------------------------------------------------------
335 * SIUMCR - SIU Module Configuration 4-31
336 *-----------------------------------------------------------------------
337 */
338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
wdenke2211742002-11-02 23:30:20 +0000340 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
341
342/*-----------------------------------------------------------------------
343 * SYPCR - System Protection Control 11-9
344 * SYPCR can only be written once after reset!
345 *-----------------------------------------------------------------------
346 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
wdenke2211742002-11-02 23:30:20 +0000349 SYPCR_SWRI | SYPCR_SWP)
350
351/*-----------------------------------------------------------------------
352 * TMCNTSC - Time Counter Status and Control 4-40
353 *-----------------------------------------------------------------------
354 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
355 * and enable Time Counter
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000358
359/*-----------------------------------------------------------------------
360 * PISCR - Periodic Interrupt Status and Control 4-42
361 *-----------------------------------------------------------------------
362 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
363 * Periodic timer
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000366
367/*-----------------------------------------------------------------------
368 * SCCR - System Clock Control 9-8
369 *-----------------------------------------------------------------------
370 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_SCCR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000372
373/*-----------------------------------------------------------------------
374 * RCCR - RISC Controller Configuration 13-7
375 *-----------------------------------------------------------------------
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000378
379/*
380 * Init Memory Controller:
381 */
382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_PSDMR 0x494D2452
384#define CONFIG_SYS_LSDMR 0x49492552
wdenke2211742002-11-02 23:30:20 +0000385
386/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
388#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000389 ORxG_BCTLD | \
390 ORxG_SCY_5_CLK)
391
392/* DPRAM to the PCI BUS on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
394#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000395 ORxG_ACS_DIV4)
396
397/* 60x Bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
399#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000400 ORxS_BPD_4 | \
401 ORxS_ROWST_PBI1_A2 | \
402 ORxS_NUMR_13 | \
403 ORxS_IBID)
404
405/* Virtex-FPGA - Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
407#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
wdenk8bde7f72003-06-27 21:31:46 +0000408 ORxG_SCY_1_CLK | \
409 ORxG_ACS_DIV2 | \
410 ORxG_CSNT )
wdenke2211742002-11-02 23:30:20 +0000411
412/* local bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
414#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000415 ORxS_BPD_4 | \
416 ORxS_ROWST_PBI1_A4 | \
417 ORxS_NUMR_13)
418
419/* DPRAM to the Sharc-Bus on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
421#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000422 ORxG_ACS_DIV4)
423
wdenke2211742002-11-02 23:30:20 +0000424#endif /* __CONFIG_H */