wdenk | 7c202ac | 2002-09-09 08:35:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | |
| 27 | /* ------------------------------------------------------------------------- */ |
| 28 | |
| 29 | |
| 30 | /* |
| 31 | * Miscelaneous platform dependent initialisations |
| 32 | */ |
| 33 | |
| 34 | int board_init (void) |
| 35 | { |
| 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
| 38 | /* memory and cpu-speed are setup before relocation */ |
| 39 | /* so we do _nothing_ here */ |
| 40 | |
| 41 | /* arch number of LART-Board */ |
wdenk | 731215e | 2004-10-10 18:41:04 +0000 | [diff] [blame] | 42 | gd->bd->bi_arch_number = MACH_TYPE_LART; |
wdenk | 7c202ac | 2002-09-09 08:35:37 +0000 | [diff] [blame] | 43 | |
| 44 | /* adress of boot parameters */ |
| 45 | gd->bd->bi_boot_params = 0xc0000100; |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | int dram_init (void) |
| 51 | { |
| 52 | DECLARE_GLOBAL_DATA_PTR; |
| 53 | bd_t *bd = gd->bd; |
| 54 | |
| 55 | bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 56 | bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 57 | bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 58 | bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
| 59 | bd->bi_dram[2].start = PHYS_SDRAM_3; |
| 60 | bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
| 61 | bd->bi_dram[3].start = PHYS_SDRAM_4; |
| 62 | bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
| 63 | |
| 64 | return (0); |
| 65 | } |