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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
wdenk85ec0bc2003-03-31 16:34:49 +000026#include <asm/arch/AT91RM9200.h>
Wolfgang Denk080bdb72005-10-05 01:51:29 +020027#include <at91rm9200_net.h>
28#include <dm9161.h>
wdenkdc7c9a12003-03-26 06:55:25 +000029
Wolfgang Denkd87080b2006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
31
wdenkdc7c9a12003-03-26 06:55:25 +000032/* ------------------------------------------------------------------------- */
33/*
34 * Miscelaneous platform dependent initialisations
35 */
36
wdenk2abbe072003-06-16 23:50:08 +000037int board_init (void)
38{
wdenk2abbe072003-06-16 23:50:08 +000039 /* Enable Ctrlc */
40 console_init_f ();
wdenkdc7c9a12003-03-26 06:55:25 +000041
wdenk2abbe072003-06-16 23:50:08 +000042 /* Correct IRDA resistor problem */
43 /* Set PA23_TXD in Output */
Wolfgang Denk27e166b2005-12-19 13:02:45 +010044 ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
wdenkdc7c9a12003-03-26 06:55:25 +000045
wdenk2abbe072003-06-16 23:50:08 +000046 /* memory and cpu-speed are setup before relocation */
47 /* so we do _nothing_ here */
48
49 /* arch number of AT91RM9200DK-Board */
wdenk731215e2004-10-10 18:41:04 +000050 gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
wdenk2abbe072003-06-16 23:50:08 +000051 /* adress of boot parameters */
52 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
53
54 return 0;
wdenkdc7c9a12003-03-26 06:55:25 +000055}
56
wdenk2abbe072003-06-16 23:50:08 +000057int dram_init (void)
wdenkdc7c9a12003-03-26 06:55:25 +000058{
wdenk2abbe072003-06-16 23:50:08 +000059 gd->bd->bi_dram[0].start = PHYS_SDRAM;
60 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
61 return 0;
wdenkdc7c9a12003-03-26 06:55:25 +000062}
63
Wolfgang Denk080bdb72005-10-05 01:51:29 +020064#ifdef CONFIG_DRIVER_ETHER
65#if (CONFIG_COMMANDS & CFG_CMD_NET)
66
67/*
68 * Name:
69 * at91rm9200_GetPhyInterface
70 * Description:
71 * Initialise the interface functions to the PHY
72 * Arguments:
73 * None
74 * Return value:
75 * None
76 */
77void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
78{
79 p_phyops->Init = dm9161_InitPhy;
80 p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
81 p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
82 p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
83}
84
85#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
86#endif /* CONFIG_DRIVER_ETHER */
87
wdenkdc7c9a12003-03-26 06:55:25 +000088/*
89 * Disk On Chip (NAND) Millenium initialization.
90 * The NAND lives in the CS2* space
91 */
92#if (CONFIG_COMMANDS & CFG_CMD_NAND)
wdenka43278a2003-09-11 19:48:06 +000093extern ulong nand_probe (ulong physadr);
wdenkdc7c9a12003-03-26 06:55:25 +000094
wdenk2abbe072003-06-16 23:50:08 +000095#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
96void nand_init (void)
wdenkdc7c9a12003-03-26 06:55:25 +000097{
98 /* Setup Smart Media, fitst enable the address range of CS3 */
wdenk2abbe072003-06-16 23:50:08 +000099 *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
100 /* set the bus interface characteristics based on
101 tDS Data Set up Time 30 - ns
102 tDH Data Hold Time 20 - ns
103 tALS ALE Set up Time 20 - ns
104 16ns at 60 MHz ~= 3 */
wdenkdc7c9a12003-03-26 06:55:25 +0000105/*memory mapping structures */
106#define SM_ID_RWH (5 << 28)
107#define SM_RWH (1 << 28)
108#define SM_RWS (0 << 24)
109#define SM_TDF (1 << 8)
110#define SM_NWS (3)
wdenk2abbe072003-06-16 23:50:08 +0000111 AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
112 AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
113 SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
wdenkdc7c9a12003-03-26 06:55:25 +0000114
wdenk2abbe072003-06-16 23:50:08 +0000115 /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
116 *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
117 AT91C_PC3_BFBAA_SMWE;
118 *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
119 AT91C_PC3_BFBAA_SMWE;
wdenkdc7c9a12003-03-26 06:55:25 +0000120
121 /* Configure PC2 as input (signal READY of the SmartMedia) */
wdenk2abbe072003-06-16 23:50:08 +0000122 *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
123 *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
wdenkdc7c9a12003-03-26 06:55:25 +0000124
125 /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
wdenk2abbe072003-06-16 23:50:08 +0000126 *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
127 *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
wdenkdc7c9a12003-03-26 06:55:25 +0000128
wdenk8b07a112004-07-10 21:45:47 +0000129 /* PIOB and PIOC clock enabling */
130 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
131 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
132
wdenk2abbe072003-06-16 23:50:08 +0000133 if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
wdenka43278a2003-09-11 19:48:06 +0000134 printf (" No SmartMedia card inserted\n");
135#ifdef DEBUG
136 printf (" SmartMedia card inserted\n");
wdenkdc7c9a12003-03-26 06:55:25 +0000137
wdenk2abbe072003-06-16 23:50:08 +0000138 printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
wdenka43278a2003-09-11 19:48:06 +0000139#endif
140 printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
wdenkdc7c9a12003-03-26 06:55:25 +0000141}
142#endif