| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | STMicroelectronics SoC DWMAC glue layer controller |
| 2 | |
| 3 | This file documents differences between the core properties in |
| 4 | Documentation/devicetree/bindings/net/stmmac.txt |
| 5 | and what is needed on STi platforms to program the stmmac glue logic. |
| 6 | |
| 7 | The device node has following properties. |
| 8 | |
| 9 | Required properties: |
| 10 | - compatible : "st,stih407-dwmac" |
| 11 | - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which |
| 12 | encompases the glue register, and the offset of the control register. |
| 13 | - st,gmac_en: this is to enable the gmac into a dedicated sysctl control |
| 14 | register available on STiH407 SoC. |
| 15 | - pinctrl-0: pin-control for all the MII mode supported. |
| 16 | |
| 17 | Optional properties: |
| 18 | - resets : phandle pointing to the system reset controller with correct |
| 19 | reset line index for ethernet reset. |
| 20 | - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or |
| 21 | MAC can generate it. |
| 22 | - st,tx-retime-src: This specifies which clk is wired up to the mac for |
| 23 | retimeing tx lines. This is totally board dependent and can take one of the |
| 24 | possible values from "txclk", "clk_125" or "clkgen". |
| 25 | If not passed, the internal clock will be used by default. |
| 26 | - sti-ethclk: this is the phy clock. |
| 27 | - sti-clkconf: this is an extra sysconfig register, available in new SoCs, |
| 28 | to program the clk retiming. |
| 29 | - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. |
| 30 | STiH407. |
| 31 | |
| 32 | Example: |
| 33 | |
| 34 | ethernet0: dwmac@9630000 { |
| 35 | device_type = "network"; |
| 36 | compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; |
| 37 | reg = <0x9630000 0x8000>; |
| 38 | reg-names = "stmmaceth"; |
| 39 | |
| 40 | st,syscon = <&syscfg_sbc_reg 0x80>; |
| 41 | st,gmac_en; |
| 42 | resets = <&softreset STIH407_ETH1_SOFTRESET>; |
| 43 | reset-names = "stmmaceth"; |
| 44 | |
| 45 | interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, |
| 46 | <GIC_SPI 99 IRQ_TYPE_NONE>, |
| 47 | <GIC_SPI 100 IRQ_TYPE_NONE>; |
| 48 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; |
| 49 | |
| 50 | snps,pbl = <32>; |
| 51 | snps,mixed-burst; |
| 52 | |
| 53 | pinctrl-names = "default"; |
| 54 | pinctrl-0 = <&pinctrl_rgmii1>; |
| 55 | |
| 56 | clock-names = "stmmaceth", "sti-ethclk"; |
| 57 | clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, |
| 58 | <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; |
| 59 | }; |