Pragnesh Patel | 01cdef2 | 2020-05-29 11:33:35 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (c) 2019 SiFive, Inc |
| 4 | * |
| 5 | * Authors: |
| 6 | * Pragnesh Patel <pragnesh.patel@sifive.com> |
| 7 | */ |
| 8 | |
| 9 | #include <init.h> |
| 10 | #include <spl.h> |
| 11 | #include <misc.h> |
| 12 | #include <log.h> |
| 13 | #include <linux/delay.h> |
Bin Meng | 3581811 | 2020-08-02 23:09:06 -0700 | [diff] [blame] | 14 | #include <linux/io.h> |
Pragnesh Patel | 01cdef2 | 2020-05-29 11:33:35 +0530 | [diff] [blame] | 15 | #include <asm/gpio.h> |
| 16 | #include <asm/arch/gpio.h> |
| 17 | #include <asm/arch/spl.h> |
| 18 | |
Bin Meng | 3581811 | 2020-08-02 23:09:06 -0700 | [diff] [blame] | 19 | #define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) |
| 20 | |
| 21 | #define MODE_SELECT_REG 0x1000 |
| 22 | #define MODE_SELECT_QSPI 0x6 |
| 23 | #define MODE_SELECT_SD 0xb |
| 24 | #define MODE_SELECT_MASK GENMASK(3, 0) |
Pragnesh Patel | 01cdef2 | 2020-05-29 11:33:35 +0530 | [diff] [blame] | 25 | |
Bin Meng | c4295ec | 2020-08-02 23:09:02 -0700 | [diff] [blame] | 26 | int spl_board_init_f(void) |
Pragnesh Patel | 01cdef2 | 2020-05-29 11:33:35 +0530 | [diff] [blame] | 27 | { |
| 28 | int ret; |
| 29 | |
Bin Meng | d6a0170 | 2020-08-02 23:09:03 -0700 | [diff] [blame] | 30 | ret = spl_soc_init(); |
Pragnesh Patel | 01cdef2 | 2020-05-29 11:33:35 +0530 | [diff] [blame] | 31 | if (ret) { |
| 32 | debug("FU540 SPL init failed: %d\n", ret); |
| 33 | return ret; |
| 34 | } |
| 35 | |
| 36 | /* |
| 37 | * GEMGXL init VSC8541 PHY reset sequence; |
| 38 | * leave pull-down active for 2ms |
| 39 | */ |
| 40 | udelay(2000); |
| 41 | ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset"); |
| 42 | if (ret) { |
| 43 | debug("gem_phy_reset gpio request failed: %d\n", ret); |
| 44 | return ret; |
| 45 | } |
| 46 | |
| 47 | /* Set GPIO 12 (PHY NRESET) */ |
| 48 | ret = gpio_direction_output(GEM_PHY_RESET, 1); |
| 49 | if (ret) { |
| 50 | debug("gem_phy_reset gpio direction set failed: %d\n", ret); |
| 51 | return ret; |
| 52 | } |
| 53 | |
| 54 | udelay(1); |
| 55 | |
| 56 | /* Reset PHY again to enter unmanaged mode */ |
| 57 | gpio_set_value(GEM_PHY_RESET, 0); |
| 58 | udelay(1); |
| 59 | gpio_set_value(GEM_PHY_RESET, 1); |
| 60 | mdelay(15); |
| 61 | |
| 62 | return 0; |
| 63 | } |
Bin Meng | 3581811 | 2020-08-02 23:09:06 -0700 | [diff] [blame] | 64 | |
| 65 | u32 spl_boot_device(void) |
| 66 | { |
| 67 | u32 mode_select = readl((void *)MODE_SELECT_REG); |
| 68 | u32 boot_device = mode_select & MODE_SELECT_MASK; |
| 69 | |
| 70 | switch (boot_device) { |
| 71 | case MODE_SELECT_QSPI: |
| 72 | return BOOT_DEVICE_SPI; |
| 73 | case MODE_SELECT_SD: |
| 74 | return BOOT_DEVICE_MMC1; |
| 75 | default: |
| 76 | debug("Unsupported boot device 0x%x but trying MMC1\n", |
| 77 | boot_device); |
| 78 | return BOOT_DEVICE_MMC1; |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | #ifdef CONFIG_SPL_LOAD_FIT |
| 83 | int board_fit_config_name_match(const char *name) |
| 84 | { |
| 85 | /* boot using first FIT config */ |
| 86 | return 0; |
| 87 | } |
| 88 | #endif |