blob: 73279c899e8cbc64dd5e2066ec98132697caee46 [file] [log] [blame]
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T4240 RDB board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_T4240RDB
14#define CONFIG_PHYS_64BIT
Chunhe Lan9a509cf2014-12-01 16:21:01 +080015#define CONFIG_DISPLAY_BOARDINFO
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080016
17#define CONFIG_FSL_SATA_V2
18#define CONFIG_PCIE4
19
20#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
21
22#ifdef CONFIG_RAMBOOT_PBL
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080023#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
24#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080025#ifndef CONFIG_SDCARD
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28#else
29#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
30#define CONFIG_SPL_ENV_SUPPORT
31#define CONFIG_SPL_SERIAL_SUPPORT
32#define CONFIG_SPL_FLUSH_IMAGE
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LIBGENERIC_SUPPORT
35#define CONFIG_SPL_LIBCOMMON_SUPPORT
36#define CONFIG_SPL_I2C_SUPPORT
37#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38#define CONFIG_FSL_LAW /* Use common FSL init code */
39#define CONFIG_SYS_TEXT_BASE 0x00201000
40#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
41#define CONFIG_SPL_PAD_TO 0x40000
42#define CONFIG_SPL_MAX_SIZE 0x28000
43#define RESET_VECTOR_OFFSET 0x27FFC
44#define BOOT_PAGE_OFFSET 0x27000
45
46#ifdef CONFIG_SDCARD
47#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
48#define CONFIG_SPL_MMC_SUPPORT
49#define CONFIG_SPL_MMC_MINIMAL
50#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
51#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
52#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
53#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
54#ifndef CONFIG_SPL_BUILD
55#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080056#endif
Chunhe Lan373762c2015-03-20 17:08:54 +080057#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
58#define CONFIG_SPL_MMC_BOOT
59#endif
60
61#ifdef CONFIG_SPL_BUILD
62#define CONFIG_SPL_SKIP_RELOCATE
63#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65#define CONFIG_SYS_NO_FLASH
66#endif
67
68#endif
69#endif /* CONFIG_RAMBOOT_PBL */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080070
71#define CONFIG_DDR_ECC
72
73#define CONFIG_CMD_REGINFO
74
75/* High Level Configuration Options */
76#define CONFIG_BOOKE
77#define CONFIG_E500 /* BOOKE e500 family */
78#define CONFIG_E500MC /* BOOKE e500mc family */
79#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
80#define CONFIG_MP /* support multiple processors */
81
82#ifndef CONFIG_SYS_TEXT_BASE
83#define CONFIG_SYS_TEXT_BASE 0xeff40000
84#endif
85
86#ifndef CONFIG_RESET_VECTOR_ADDRESS
87#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
88#endif
89
90#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
91#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
92#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053093#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080094#define CONFIG_PCI /* Enable PCI/PCIE */
95#define CONFIG_PCIE1 /* PCIE controler 1 */
96#define CONFIG_PCIE2 /* PCIE controler 2 */
97#define CONFIG_PCIE3 /* PCIE controler 3 */
98#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
99#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
100
101#define CONFIG_FSL_LAW /* Use common FSL init code */
102
103#define CONFIG_ENV_OVERWRITE
104
105/*
106 * These can be toggled for performance analysis, otherwise use default.
107 */
108#define CONFIG_SYS_CACHE_STASHING
109#define CONFIG_BTB /* toggle branch predition */
110#ifdef CONFIG_DDR_ECC
111#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
112#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
113#endif
114
115#define CONFIG_ENABLE_36BIT_PHYS
116
117#define CONFIG_ADDR_MAP
118#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
119
120#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
121#define CONFIG_SYS_MEMTEST_END 0x00400000
122#define CONFIG_SYS_ALT_MEMTEST
123#define CONFIG_PANIC_HANG /* do not reset board on panic */
124
125/*
126 * Config the L3 Cache as L3 SRAM
127 */
Chunhe Lan373762c2015-03-20 17:08:54 +0800128#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
129#define CONFIG_SYS_L3_SIZE (512 << 10)
130#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
131#ifdef CONFIG_RAMBOOT_PBL
132#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
133#endif
134#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
135#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
136#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
137#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800138
139#define CONFIG_SYS_DCSRBAR 0xf0000000
140#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
141
142/*
143 * DDR Setup
144 */
145#define CONFIG_VERY_BIG_RAM
146#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148
149/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
150#define CONFIG_DIMM_SLOTS_PER_CTLR 1
151#define CONFIG_CHIP_SELECTS_PER_CTRL 4
152#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
153
154#define CONFIG_DDR_SPD
155#define CONFIG_SYS_FSL_DDR3
156
157
158/*
159 * IFC Definitions
160 */
161#define CONFIG_SYS_FLASH_BASE 0xe0000000
162#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
163
164
Chunhe Lan373762c2015-03-20 17:08:54 +0800165#ifdef CONFIG_SPL_BUILD
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
167#else
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Chunhe Lan373762c2015-03-20 17:08:54 +0800169#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800170
171#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
172#define CONFIG_MISC_INIT_R
173
174#define CONFIG_HWCONFIG
175
176/* define to use L1 as initial stack */
177#define CONFIG_L1_INIT_RAM
178#define CONFIG_SYS_INIT_RAM_LOCK
179#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
180#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700181#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800182/* The assembler doesn't like typecast */
183#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
184 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
185 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
186#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
187
188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
189 GENERATED_GBL_DATA_SIZE)
190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
191
Chunhe Lan373762c2015-03-20 17:08:54 +0800192#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800193#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
194
195/* Serial Port - controlled on board with jumper J8
196 * open - index 2
197 * shorted - index 1
198 */
199#define CONFIG_CONS_INDEX 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800200#define CONFIG_SYS_NS16550_SERIAL
201#define CONFIG_SYS_NS16550_REG_SIZE 1
202#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
203
204#define CONFIG_SYS_BAUDRATE_TABLE \
205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
206
207#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
208#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
209#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
210#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
211
212/* Use the HUSH parser */
213#define CONFIG_SYS_HUSH_PARSER
214#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
215
216/* pass open firmware flat tree */
217#define CONFIG_OF_LIBFDT
218#define CONFIG_OF_BOARD_SETUP
219#define CONFIG_OF_STDOUT_VIA_ALIAS
220
221/* new uImage format support */
222#define CONFIG_FIT
223#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
224
225/* I2C */
226#define CONFIG_SYS_I2C
227#define CONFIG_SYS_I2C_FSL
228#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
229#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
230#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
232
233/*
234 * General PCI
235 * Memory space is mapped 1-1, but I/O space must start from 0.
236 */
237
238/* controller 1, direct to uli, tgtid 3, Base address 20000 */
239#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
240#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
241#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
242#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
243#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
244#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
245#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
246#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
247
248/* controller 2, Slot 2, tgtid 2, Base address 201000 */
249#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
250#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
251#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
252#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
253#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
254#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
255#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
256#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
257
258/* controller 3, Slot 1, tgtid 1, Base address 202000 */
259#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
260#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
261#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
262#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
263#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
264#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
265#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
266#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
267
268/* controller 4, Base address 203000 */
269#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
270#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
271#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
272#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
273#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
274#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
275
276#ifdef CONFIG_PCI
277#define CONFIG_PCI_INDIRECT_BRIDGE
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800278#define CONFIG_PCI_PNP /* do pci plug-and-play */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800279
280#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
281#define CONFIG_DOS_PARTITION
282#endif /* CONFIG_PCI */
283
284/* SATA */
285#ifdef CONFIG_FSL_SATA_V2
286#define CONFIG_LIBATA
287#define CONFIG_FSL_SATA
288
289#define CONFIG_SYS_SATA_MAX_DEVICE 2
290#define CONFIG_SATA1
291#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
292#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
293#define CONFIG_SATA2
294#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
295#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
296
297#define CONFIG_LBA48
298#define CONFIG_CMD_SATA
299#define CONFIG_DOS_PARTITION
300#define CONFIG_CMD_EXT2
301#endif
302
303#ifdef CONFIG_FMAN_ENET
304#define CONFIG_MII /* MII PHY management */
305#define CONFIG_ETHPRIME "FM1@DTSEC1"
306#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
307#endif
308
309/*
310 * Environment
311 */
312#define CONFIG_LOADS_ECHO /* echo on for serial download */
313#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
314
315/*
316 * Command line configuration.
317 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800318#define CONFIG_CMD_DHCP
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800319#define CONFIG_CMD_ERRATA
320#define CONFIG_CMD_GREPENV
321#define CONFIG_CMD_IRQ
322#define CONFIG_CMD_I2C
323#define CONFIG_CMD_MII
324#define CONFIG_CMD_PING
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800325
326#ifdef CONFIG_PCI
327#define CONFIG_CMD_PCI
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800328#endif
329
330/*
331 * Miscellaneous configurable options
332 */
333#define CONFIG_SYS_LONGHELP /* undef to save memory */
334#define CONFIG_CMDLINE_EDITING /* Command-line editing */
335#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
336#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
337#ifdef CONFIG_CMD_KGDB
338#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
339#else
340#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
341#endif
342#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
343#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
344#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
345
346/*
347 * For booting Linux, the board info and command line data
348 * have to be in the first 64 MB of memory, since this is
349 * the maximum mapped by the Linux kernel during initialization.
350 */
351#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
352#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
353
354#ifdef CONFIG_CMD_KGDB
355#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
356#endif
357
358/*
359 * Environment Configuration
360 */
361#define CONFIG_ROOTPATH "/opt/nfsroot"
362#define CONFIG_BOOTFILE "uImage"
363#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
364
365/* default location for tftp and bootm */
366#define CONFIG_LOADADDR 1000000
367
368
369#define CONFIG_BAUDRATE 115200
370
371#define CONFIG_HVBOOT \
372 "setenv bootargs config-addr=0x60000000; " \
373 "bootm 0x01000000 - 0x00f00000"
374
375#ifdef CONFIG_SYS_NO_FLASH
376#ifndef CONFIG_RAMBOOT_PBL
377#define CONFIG_ENV_IS_NOWHERE
378#endif
379#else
380#define CONFIG_FLASH_CFI_DRIVER
381#define CONFIG_SYS_FLASH_CFI
382#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
383#endif
384
385#if defined(CONFIG_SPIFLASH)
386#define CONFIG_SYS_EXTRA_ENV_RELOC
387#define CONFIG_ENV_IS_IN_SPI_FLASH
388#define CONFIG_ENV_SPI_BUS 0
389#define CONFIG_ENV_SPI_CS 0
390#define CONFIG_ENV_SPI_MAX_HZ 10000000
391#define CONFIG_ENV_SPI_MODE 0
392#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
393#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
394#define CONFIG_ENV_SECT_SIZE 0x10000
395#elif defined(CONFIG_SDCARD)
396#define CONFIG_SYS_EXTRA_ENV_RELOC
397#define CONFIG_ENV_IS_IN_MMC
398#define CONFIG_SYS_MMC_ENV_DEV 0
399#define CONFIG_ENV_SIZE 0x2000
Chunhe Lan373762c2015-03-20 17:08:54 +0800400#define CONFIG_ENV_OFFSET (512 * 0x800)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800401#elif defined(CONFIG_NAND)
402#define CONFIG_SYS_EXTRA_ENV_RELOC
403#define CONFIG_ENV_IS_IN_NAND
404#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
405#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
406#elif defined(CONFIG_ENV_IS_NOWHERE)
407#define CONFIG_ENV_SIZE 0x2000
408#else
409#define CONFIG_ENV_IS_IN_FLASH
410#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
411#define CONFIG_ENV_SIZE 0x2000
412#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
413#endif
414
415#define CONFIG_SYS_CLK_FREQ 66666666
416#define CONFIG_DDR_CLK_FREQ 133333333
417
418#ifndef __ASSEMBLY__
419unsigned long get_board_sys_clk(void);
420unsigned long get_board_ddr_clk(void);
421#endif
422
423/*
424 * DDR Setup
425 */
426#define CONFIG_SYS_SPD_BUS_NUM 0
427#define SPD_EEPROM_ADDRESS1 0x52
428#define SPD_EEPROM_ADDRESS2 0x54
429#define SPD_EEPROM_ADDRESS3 0x56
430#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
431#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
432
433/*
434 * IFC Definitions
435 */
436#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
437#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
438 + 0x8000000) | \
439 CSPR_PORT_SIZE_16 | \
440 CSPR_MSEL_NOR | \
441 CSPR_V)
442#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
443#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
444 CSPR_PORT_SIZE_16 | \
445 CSPR_MSEL_NOR | \
446 CSPR_V)
447#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
448/* NOR Flash Timing Params */
449#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
450
451#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
452 FTIM0_NOR_TEADC(0x5) | \
453 FTIM0_NOR_TEAHC(0x5))
454#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
455 FTIM1_NOR_TRAD_NOR(0x1A) |\
456 FTIM1_NOR_TSEQRAD_NOR(0x13))
457#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
458 FTIM2_NOR_TCH(0x4) | \
459 FTIM2_NOR_TWPH(0x0E) | \
460 FTIM2_NOR_TWP(0x1c))
461#define CONFIG_SYS_NOR_FTIM3 0x0
462
463#define CONFIG_SYS_FLASH_QUIET_TEST
464#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
465
466#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
467#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
468#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
469#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
470
471#define CONFIG_SYS_FLASH_EMPTY_INFO
472#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
473 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
474
475/* NAND Flash on IFC */
476#define CONFIG_NAND_FSL_IFC
477#define CONFIG_SYS_NAND_MAX_ECCPOS 256
478#define CONFIG_SYS_NAND_MAX_OOBFREE 2
479#define CONFIG_SYS_NAND_BASE 0xff800000
480#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
481
482#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
483#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
484 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
485 | CSPR_MSEL_NAND /* MSEL = NAND */ \
486 | CSPR_V)
487#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
488
489#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
490 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
491 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
492 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
493 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
494 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
495 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
496
497#define CONFIG_SYS_NAND_ONFI_DETECTION
498
499/* ONFI NAND Flash mode0 Timing Params */
500#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
501 FTIM0_NAND_TWP(0x18) | \
502 FTIM0_NAND_TWCHT(0x07) | \
503 FTIM0_NAND_TWH(0x0a))
504#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
505 FTIM1_NAND_TWBE(0x39) | \
506 FTIM1_NAND_TRR(0x0e) | \
507 FTIM1_NAND_TRP(0x18))
508#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
509 FTIM2_NAND_TREH(0x0a) | \
510 FTIM2_NAND_TWHRE(0x1e))
511#define CONFIG_SYS_NAND_FTIM3 0x0
512
513#define CONFIG_SYS_NAND_DDR_LAW 11
514#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
515#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800516#define CONFIG_CMD_NAND
517
518#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
519
520#if defined(CONFIG_NAND)
521#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
522#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
523#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
524#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
525#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
526#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
527#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
528#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
529#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
530#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
531#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
532#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
533#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
534#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
535#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
536#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
537#else
538#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
539#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
540#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
541#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
542#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
543#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
544#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
545#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
546#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
547#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
548#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
549#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
550#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
551#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
552#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
553#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
554#endif
555#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
556#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
557#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
558#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
559#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
560#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
561#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
562#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
563
Chunhe Lanab06b232014-09-12 14:47:09 +0800564/* CPLD on IFC */
565#define CONFIG_SYS_CPLD_BASE 0xffdf0000
566#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
567#define CONFIG_SYS_CSPR3_EXT (0xf)
568#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
569 | CSPR_PORT_SIZE_8 \
570 | CSPR_MSEL_GPCM \
571 | CSPR_V)
572
573#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
574#define CONFIG_SYS_CSOR3 0x0
575
576/* CPLD Timing parameters for IFC CS3 */
577#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
578 FTIM0_GPCM_TEADC(0x0e) | \
579 FTIM0_GPCM_TEAHC(0x0e))
580#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
581 FTIM1_GPCM_TRAD(0x1f))
582#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Chunhe Lan1b5c2b52014-10-20 16:03:15 +0800583 FTIM2_GPCM_TCH(0x8) | \
Chunhe Lanab06b232014-09-12 14:47:09 +0800584 FTIM2_GPCM_TWP(0x1f))
585#define CONFIG_SYS_CS3_FTIM3 0x0
586
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800587#if defined(CONFIG_RAMBOOT_PBL)
588#define CONFIG_SYS_RAMBOOT
589#endif
590
591
592/* I2C */
593#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
594#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
595#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
596#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
597
598#define I2C_MUX_CH_DEFAULT 0x8
599#define I2C_MUX_CH_VOL_MONITOR 0xa
600#define I2C_MUX_CH_VSC3316_FS 0xc
601#define I2C_MUX_CH_VSC3316_BS 0xd
602
603/* Voltage monitor on channel 2*/
604#define I2C_VOL_MONITOR_ADDR 0x40
605#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
606#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
607#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
608
609/*
610 * eSPI - Enhanced SPI
611 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800612#define CONFIG_CMD_SF
613#define CONFIG_SF_DEFAULT_SPEED 10000000
614#define CONFIG_SF_DEFAULT_MODE 0
615
616
617/* Qman/Bman */
618#ifndef CONFIG_NOBQFMAN
619#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
620#define CONFIG_SYS_BMAN_NUM_PORTALS 50
621#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
622#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
623#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500624#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
625#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
626#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
627#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
628#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
629 CONFIG_SYS_BMAN_CENA_SIZE)
630#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
631#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800632#define CONFIG_SYS_QMAN_NUM_PORTALS 50
633#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
634#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
635#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500636#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
637#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
638#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
639#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
640#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
641 CONFIG_SYS_QMAN_CENA_SIZE)
642#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
643#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800644
645#define CONFIG_SYS_DPAA_FMAN
646#define CONFIG_SYS_DPAA_PME
647#define CONFIG_SYS_PMAN
648#define CONFIG_SYS_DPAA_DCE
649#define CONFIG_SYS_DPAA_RMAN
650#define CONFIG_SYS_INTERLAKEN
651
652/* Default address of microcode for the Linux Fman driver */
653#if defined(CONFIG_SPIFLASH)
654/*
655 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
656 * env, so we got 0x110000.
657 */
658#define CONFIG_SYS_QE_FW_IN_SPIFLASH
659#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
660#elif defined(CONFIG_SDCARD)
661/*
662 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Chunhe Lan373762c2015-03-20 17:08:54 +0800663 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
664 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800665 */
666#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Chunhe Lan373762c2015-03-20 17:08:54 +0800667#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800668#elif defined(CONFIG_NAND)
669#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
670#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
671#else
672#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
673#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
674#endif
675#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
676#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
677#endif /* CONFIG_NOBQFMAN */
678
679#ifdef CONFIG_SYS_DPAA_FMAN
680#define CONFIG_FMAN_ENET
681#define CONFIG_PHYLIB_10G
682#define CONFIG_PHY_VITESSE
683#define CONFIG_PHY_CORTINA
Chunhe Lana8efe792015-03-24 15:10:41 +0800684#define CONFIG_SYS_CORTINA_FW_IN_NOR
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800685#define CONFIG_CORTINA_FW_ADDR 0xefe00000
686#define CONFIG_CORTINA_FW_LENGTH 0x40000
687#define CONFIG_PHY_TERANETICS
688#define SGMII_PHY_ADDR1 0x0
689#define SGMII_PHY_ADDR2 0x1
690#define SGMII_PHY_ADDR3 0x2
691#define SGMII_PHY_ADDR4 0x3
692#define SGMII_PHY_ADDR5 0x4
693#define SGMII_PHY_ADDR6 0x5
694#define SGMII_PHY_ADDR7 0x6
695#define SGMII_PHY_ADDR8 0x7
696#define FM1_10GEC1_PHY_ADDR 0x10
697#define FM1_10GEC2_PHY_ADDR 0x11
698#define FM2_10GEC1_PHY_ADDR 0x12
699#define FM2_10GEC2_PHY_ADDR 0x13
700#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
701#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
702#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
703#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
704#endif
705
706
707/* SATA */
708#ifdef CONFIG_FSL_SATA_V2
709#define CONFIG_LIBATA
710#define CONFIG_FSL_SATA
711
712#define CONFIG_SYS_SATA_MAX_DEVICE 2
713#define CONFIG_SATA1
714#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
715#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
716#define CONFIG_SATA2
717#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
718#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
719
720#define CONFIG_LBA48
721#define CONFIG_CMD_SATA
722#define CONFIG_DOS_PARTITION
723#define CONFIG_CMD_EXT2
724#endif
725
726#ifdef CONFIG_FMAN_ENET
727#define CONFIG_MII /* MII PHY management */
728#define CONFIG_ETHPRIME "FM1@DTSEC1"
729#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
730#endif
731
732/*
733* USB
734*/
735#define CONFIG_CMD_USB
736#define CONFIG_USB_STORAGE
737#define CONFIG_USB_EHCI
738#define CONFIG_USB_EHCI_FSL
739#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
740#define CONFIG_CMD_EXT2
741#define CONFIG_HAS_FSL_DR_USB
742
743#define CONFIG_MMC
744
745#ifdef CONFIG_MMC
746#define CONFIG_FSL_ESDHC
747#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
748#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
749#define CONFIG_CMD_MMC
750#define CONFIG_GENERIC_MMC
751#define CONFIG_CMD_EXT2
752#define CONFIG_CMD_FAT
753#define CONFIG_DOS_PARTITION
Xiaobo Xie929dfdc2014-11-18 09:12:24 +0800754#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800755#endif
756
Ruchika Gupta737537e2014-10-15 11:35:31 +0530757/* Hash command with SHA acceleration supported in hardware */
758#ifdef CONFIG_FSL_CAAM
759#define CONFIG_CMD_HASH
760#define CONFIG_SHA_HW_ACCEL
761#endif
762
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800763#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
764
765#define __USB_PHY_TYPE utmi
766
767/*
768 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
769 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
770 * interleaving. It can be cacheline, page, bank, superbank.
771 * See doc/README.fsl-ddr for details.
772 */
Chunhe Lan1a344452014-05-07 10:56:18 +0800773#ifdef CONFIG_PPC_T4240
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800774#define CTRL_INTLV_PREFERED 3way_4KB
Chunhe Lan1a344452014-05-07 10:56:18 +0800775#else
776#define CTRL_INTLV_PREFERED cacheline
777#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800778
779#define CONFIG_EXTRA_ENV_SETTINGS \
780 "hwconfig=fsl_ddr:" \
781 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
782 "bank_intlv=auto;" \
783 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
784 "netdev=eth0\0" \
785 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
786 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
787 "tftpflash=tftpboot $loadaddr $uboot && " \
788 "protect off $ubootaddr +$filesize && " \
789 "erase $ubootaddr +$filesize && " \
790 "cp.b $loadaddr $ubootaddr $filesize && " \
791 "protect on $ubootaddr +$filesize && " \
792 "cmp.b $loadaddr $ubootaddr $filesize\0" \
793 "consoledev=ttyS0\0" \
794 "ramdiskaddr=2000000\0" \
795 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
796 "fdtaddr=c00000\0" \
797 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
798 "bdev=sda3\0"
799
800#define CONFIG_HVBOOT \
801 "setenv bootargs config-addr=0x60000000; " \
802 "bootm 0x01000000 - 0x00f00000"
803
804#define CONFIG_LINUX \
805 "setenv bootargs root=/dev/ram rw " \
806 "console=$consoledev,$baudrate $othbootargs;" \
807 "setenv ramdiskaddr 0x02000000;" \
808 "setenv fdtaddr 0x00c00000;" \
809 "setenv loadaddr 0x1000000;" \
810 "bootm $loadaddr $ramdiskaddr $fdtaddr"
811
812#define CONFIG_HDBOOT \
813 "setenv bootargs root=/dev/$bdev rw " \
814 "console=$consoledev,$baudrate $othbootargs;" \
815 "tftp $loadaddr $bootfile;" \
816 "tftp $fdtaddr $fdtfile;" \
817 "bootm $loadaddr - $fdtaddr"
818
819#define CONFIG_NFSBOOTCOMMAND \
820 "setenv bootargs root=/dev/nfs rw " \
821 "nfsroot=$serverip:$rootpath " \
822 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
823 "console=$consoledev,$baudrate $othbootargs;" \
824 "tftp $loadaddr $bootfile;" \
825 "tftp $fdtaddr $fdtfile;" \
826 "bootm $loadaddr - $fdtaddr"
827
828#define CONFIG_RAMBOOTCOMMAND \
829 "setenv bootargs root=/dev/ram rw " \
830 "console=$consoledev,$baudrate $othbootargs;" \
831 "tftp $ramdiskaddr $ramdiskfile;" \
832 "tftp $loadaddr $bootfile;" \
833 "tftp $fdtaddr $fdtfile;" \
834 "bootm $loadaddr $ramdiskaddr $fdtaddr"
835
836#define CONFIG_BOOTCOMMAND CONFIG_LINUX
837
838#include <asm/fsl_secure_boot.h>
839
840#ifdef CONFIG_SECURE_BOOT
841/* Secure Boot target was not getting build for T4240 because of
842 * increased binary size. So the size is being reduced by removing USB
843 * which is anyways not used in Secure Environment.
844 */
845#undef CONFIG_CMD_USB
Ruchika Gupta789490b2014-10-07 15:48:46 +0530846#define CONFIG_CMD_BLOB
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800847#endif
848
849#endif /* __CONFIG_H */