blob: 8771cdc8ca0a3eaf109a63e44225ba4ba5eb5b92 [file] [log] [blame]
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +01001/*
2 * (C) Copyright 2014
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_MPC83xx 1 /* MPC83xx family */
17#define CONFIG_MPC830x 1 /* MPC830x family */
18#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19#define CONFIG_STRIDER 1 /* STRIDER board specific */
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
23#ifdef CONFIG_STRIDER_CPU
24#define CONFIG_IDENT_STRING " strider cpu 0.01"
25#else
26#define CONFIG_IDENT_STRING " strider con 0.01"
27#endif
28
29#define CONFIG_BOARD_EARLY_INIT_F
30#define CONFIG_BOARD_EARLY_INIT_R
31#define CONFIG_LAST_STAGE_INIT
32
33/* new uImage format support */
34#define CONFIG_FIT 1
35#define CONFIG_FIT_VERBOSE 1
36
37#define CONFIG_MMC
38#define CONFIG_FSL_ESDHC
39#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
40#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
41
42#define CONFIG_CMD_MMC
43#define CONFIG_GENERIC_MMC
44#define CONFIG_DOS_PARTITION
45#define CONFIG_CMD_EXT2
46
47#define CONFIG_CMD_MEMTEST
48#define CONFIG_SYS_ALT_MEMTEST
49
50#define CONFIG_CMD_FPGAD
51#define CONFIG_CMD_IOLOOP
52
53/*
54 * System Clock Setup
55 */
56#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
57#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
58
59/*
60 * Hardware Reset Configuration Word
61 * if CLKIN is 66.66MHz, then
62 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
63 * We choose the A type silicon as default, so the core is 400Mhz.
64 */
65#define CONFIG_SYS_HRCW_LOW (\
66 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
67 HRCWL_DDR_TO_SCB_CLK_2X1 |\
68 HRCWL_SVCOD_DIV_2 |\
69 HRCWL_CSB_TO_CLKIN_4X1 |\
70 HRCWL_CORE_TO_CSB_3X1)
71/*
72 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
73 * in 8308's HRCWH according to the manual, but original Freescale's
74 * code has them and I've expirienced some problems using the board
75 * with BDI3000 attached when I've tried to set these bits to zero
76 * (UART doesn't work after the 'reset run' command).
77 */
78#define CONFIG_SYS_HRCW_HIGH (\
79 HRCWH_PCI_HOST |\
80 HRCWH_PCI1_ARBITER_ENABLE |\
81 HRCWH_CORE_ENABLE |\
82 HRCWH_FROM_0XFFF00100 |\
83 HRCWH_BOOTSEQ_DISABLE |\
84 HRCWH_SW_WATCHDOG_DISABLE |\
85 HRCWH_ROM_LOC_LOCAL_16BIT |\
86 HRCWH_RL_EXT_LEGACY |\
87 HRCWH_TSEC1M_IN_MII |\
88 HRCWH_TSEC2M_IN_RGMII |\
89 HRCWH_BIG_ENDIAN)
90
91/*
92 * System IO Config
93 */
94#define CONFIG_SYS_SICRH (\
95 SICRH_ESDHC_A_SD |\
96 SICRH_ESDHC_B_SD |\
97 SICRH_ESDHC_C_SD |\
98 SICRH_GPIO_A_GPIO |\
99 SICRH_GPIO_B_GPIO |\
100 SICRH_IEEE1588_A_GPIO |\
101 SICRH_USB |\
102 SICRH_GTM_GPIO |\
103 SICRH_IEEE1588_B_GPIO |\
104 SICRH_ETSEC2_GPIO |\
105 SICRH_GPIOSEL_1 |\
106 SICRH_TMROBI_V3P3 |\
107 SICRH_TSOBI1_V2P5 |\
108 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
109#define CONFIG_SYS_SICRL (\
110 SICRL_SPI_PF0 |\
111 SICRL_UART_PF0 |\
112 SICRL_IRQ_PF0 |\
113 SICRL_I2C2_PF0 |\
114 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
115
116/*
117 * IMMR new address
118 */
119#define CONFIG_SYS_IMMR 0xE0000000
120
121/*
122 * SERDES
123 */
124#define CONFIG_FSL_SERDES
125#define CONFIG_FSL_SERDES1 0xe3000
126
127/*
128 * Arbiter Setup
129 */
130#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
131#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
132#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
133
134/*
135 * DDR Setup
136 */
137#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
139#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
140#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
141#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
142 | DDRCDR_PZ_LOZ \
143 | DDRCDR_NZ_LOZ \
144 | DDRCDR_ODT \
145 | DDRCDR_Q_DRN)
146 /* 0x7b880001 */
147/*
148 * Manually set up DDR parameters
149 * consist of one chip NT5TU64M16HG from NANYA
150 */
151
152#define CONFIG_SYS_DDR_SIZE 128 /* MB */
153
154#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
155#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
156 | CSCONFIG_ODT_RD_NEVER \
157 | CSCONFIG_ODT_WR_ONLY_CURRENT \
158 | CSCONFIG_BANK_BIT_3 \
159 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
160 /* 0x80010102 */
161#define CONFIG_SYS_DDR_TIMING_3 0
162#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
163 | (0 << TIMING_CFG0_WRT_SHIFT) \
164 | (0 << TIMING_CFG0_RRT_SHIFT) \
165 | (0 << TIMING_CFG0_WWT_SHIFT) \
166 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
167 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
168 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
169 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
170 /* 0x00260802 */
171#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
172 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
173 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
174 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
175 | (9 << TIMING_CFG1_REFREC_SHIFT) \
176 | (2 << TIMING_CFG1_WRREC_SHIFT) \
177 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
178 | (2 << TIMING_CFG1_WRTORD_SHIFT))
179 /* 0x26279222 */
180#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
181 | (4 << TIMING_CFG2_CPO_SHIFT) \
182 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
183 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
184 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
185 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
186 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
187 /* 0x021848c5 */
188#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
189 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
190 /* 0x08240100 */
191#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
192 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
193 | SDRAM_CFG_DBW_16)
194 /* 0x43100000 */
195
196#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
197#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
198 | (0x0242 << SDRAM_MODE_SD_SHIFT))
199 /* ODT 150ohm CL=4, AL=0 on SDRAM */
200#define CONFIG_SYS_DDR_MODE2 0x00000000
201
202/*
203 * Memory test
204 */
205#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
206#define CONFIG_SYS_MEMTEST_END 0x07f00000
207
208/*
209 * The reserved memory
210 */
211#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
212
213#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
214#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
215
216/*
217 * Initial RAM Base Address Setup
218 */
219#define CONFIG_SYS_INIT_RAM_LOCK 1
220#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
221#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
222#define CONFIG_SYS_GBL_DATA_OFFSET \
223 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
224
225/*
226 * Local Bus Configuration & Clock Setup
227 */
228#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
229#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
230#define CONFIG_SYS_LBC_LBCR 0x00040000
231
232/*
233 * FLASH on the Local Bus
234 */
235#if 1
236#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
237#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
238#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
239#define CONFIG_FLASH_CFI_LEGACY
240#define CONFIG_SYS_FLASH_LEGACY_512Kx16
241#else
242#define CONFIG_SYS_NO_FLASH
243#endif
244
245#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
246#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
247#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
248
249/* Window base at flash base */
250#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
251#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
252
253#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
254 | BR_PS_16 /* 16 bit port */ \
255 | BR_MS_GPCM /* MSEL = GPCM */ \
256 | BR_V) /* valid */
257#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
258 | OR_UPM_XAM \
259 | OR_GPCM_CSNT \
260 | OR_GPCM_ACS_DIV2 \
261 | OR_GPCM_XACS \
262 | OR_GPCM_SCY_15 \
263 | OR_GPCM_TRLX_SET \
264 | OR_GPCM_EHTR_SET)
265
266#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
267#define CONFIG_SYS_MAX_FLASH_SECT 135
268
269#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
270#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
271
272/*
273 * FPGA
274 */
275#define CONFIG_SYS_FPGA0_BASE 0xE0600000
276#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
277
278/* Window base at FPGA base */
279#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
280#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
281
282#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
283 | BR_PS_16 /* 16 bit port */ \
284 | BR_MS_GPCM /* MSEL = GPCM */ \
285 | BR_V) /* valid */
286#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
287 | OR_UPM_XAM \
288 | OR_GPCM_CSNT \
289 | OR_GPCM_ACS_DIV2 \
290 | OR_GPCM_XACS \
291 | OR_GPCM_SCY_15 \
292 | OR_GPCM_TRLX_SET \
293 | OR_GPCM_EHTR_SET)
294
295#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
296#define CONFIG_SYS_FPGA_DONE(k) 0x0010
297
298#define CONFIG_SYS_FPGA_COUNT 1
299
300#define CONFIG_SYS_MCLINK_MAX 3
301
302#define CONFIG_SYS_FPGA_PTR \
303 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
304
305#define CONFIG_SYS_FPGA_NO_RFL_HI
306
307/*
308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 2
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +0100311#define CONFIG_SYS_NS16550_SERIAL
312#define CONFIG_SYS_NS16550_REG_SIZE 1
313#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
314
315#define CONFIG_SYS_BAUDRATE_TABLE \
316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
317
318#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
319#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
320
321/* Use the HUSH parser */
322#define CONFIG_SYS_HUSH_PARSER
323
324/* Pass open firmware flat tree */
325#define CONFIG_OF_LIBFDT 1
326#define CONFIG_OF_BOARD_SETUP 1
327#define CONFIG_OF_STDOUT_VIA_ALIAS 1
328
329/* I2C */
330#define CONFIG_SYS_I2C
331#define CONFIG_SYS_I2C_FSL
332#define CONFIG_SYS_FSL_I2C_SPEED 400000
333#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
334#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
335
336#define CONFIG_PCA953X /* NXP PCA9554 */
337#define CONFIG_PCA9698 /* NXP PCA9698 */
338
339#define CONFIG_SYS_I2C_IHS
340#define CONFIG_SYS_I2C_IHS_CH0
341#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
342#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
343#define CONFIG_SYS_I2C_IHS_CH1
344#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
345#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
346#define CONFIG_SYS_I2C_IHS_CH2
347#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
348#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
349#define CONFIG_SYS_I2C_IHS_CH3
350#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
351#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
352
353/*
354 * Software (bit-bang) I2C driver configuration
355 */
356#define CONFIG_SYS_I2C_SOFT
357#define CONFIG_SOFT_I2C_READ_REPEATED_START
358#define CONFIG_SYS_I2C_SOFT_SPEED 50000
359#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
360#define I2C_SOFT_DECLARATIONS2
361#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
362#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
363#define I2C_SOFT_DECLARATIONS3
364#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
365#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
366#define I2C_SOFT_DECLARATIONS4
367#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
368#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
369#ifdef CONFIG_STRIDER_CON
370#define I2C_SOFT_DECLARATIONS5
371#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
372#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
373#define I2C_SOFT_DECLARATIONS6
374#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
375#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
376#define I2C_SOFT_DECLARATIONS7
377#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
378#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
379#define I2C_SOFT_DECLARATIONS8
380#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
381#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
382#endif
383
384#ifdef CONFIG_STRIDER_CON
385#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
386#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
387#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
388#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
389#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
390 {12, 0x4c} }
391#else
392#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
393#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
394#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
395#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
396 {4, 0x18} }
397#endif
398
399#ifndef __ASSEMBLY__
400void fpga_gpio_set(unsigned int bus, int pin);
401void fpga_gpio_clear(unsigned int bus, int pin);
402int fpga_gpio_get(unsigned int bus, int pin);
403#endif
404
405#ifdef CONFIG_STRIDER_CON
406#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
407#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
408#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
409 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
410#else
411#define I2C_SDA_GPIO 0x0040
412#define I2C_SCL_GPIO 0x0020
413#define I2C_FPGA_IDX I2C_ADAP_HWNR
414#endif
415#define I2C_ACTIVE { }
416#define I2C_TRISTATE { }
417#define I2C_READ \
418 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
419#define I2C_SDA(bit) \
420 do { \
421 if (bit) \
422 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
423 else \
424 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
425 } while (0)
426#define I2C_SCL(bit) \
427 do { \
428 if (bit) \
429 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
430 else \
431 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
432 } while (0)
433#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
434
435/*
436 * Software (bit-bang) MII driver configuration
437 */
438#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
439#define CONFIG_BITBANGMII_MULTI
440
441/*
442 * OSD Setup
443 */
444#define CONFIG_SYS_OSD_SCREENS 1
445#define CONFIG_SYS_DP501_DIFFERENTIAL
446#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
447
448/*
449 * General PCI
450 * Addresses are mapped 1-1.
451 */
452#define CONFIG_SYS_PCIE1_BASE 0xA0000000
453#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
454#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
455#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
456#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
457#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
458#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
459#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
460#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
461
462/* enable PCIE clock */
463#define CONFIG_SYS_SCCR_PCIEXP1CM 1
464
465#define CONFIG_PCI
466#define CONFIG_PCI_INDIRECT_BRIDGE
467#define CONFIG_PCIE
468
469#define CONFIG_PCI_PNP /* do pci plug-and-play */
470
471#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
472#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
473
474/*
475 * TSEC
476 */
477#define CONFIG_TSEC_ENET /* TSEC ethernet support */
478#define CONFIG_SYS_TSEC1_OFFSET 0x24000
479#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
480
481/*
482 * TSEC ethernet configuration
483 */
484#define CONFIG_MII 1 /* MII PHY management */
485#define CONFIG_TSEC1
486#define CONFIG_TSEC1_NAME "eTSEC0"
487#define TSEC1_PHY_ADDR 1
488#define TSEC1_PHYIDX 0
489#define TSEC1_FLAGS 0
490
491/* Options are: eTSEC[0-1] */
492#define CONFIG_ETHPRIME "eTSEC0"
493
494/*
495 * Environment
496 */
497#if 1
498#define CONFIG_ENV_IS_IN_FLASH 1
499#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
500 CONFIG_SYS_MONITOR_LEN)
501#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
502#define CONFIG_ENV_SIZE 0x2000
503#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
504#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
505#else
506#define CONFIG_ENV_IS_NOWHERE
507#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
508#endif
509
510#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
511#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
512
513/*
514 * Command line configuration.
515 */
516#define CONFIG_CMD_I2C
517#define CONFIG_CMD_MII
518#define CONFIG_CMD_PCI
519#define CONFIG_CMD_PING
520
521#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
522#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
523
524/*
525 * Miscellaneous configurable options
526 */
527#define CONFIG_SYS_LONGHELP /* undef to save memory */
528#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
529#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
530
531#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
532
533#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
534
535#define CONFIG_SYS_CONSOLE_INFO_QUIET
536
537/* Print Buffer Size */
538#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
539#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
540#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
541
542/*
543 * For booting Linux, the board info and command line data
544 * have to be in the first 256 MB of memory, since this is
545 * the maximum mapped by the Linux kernel during initialization.
546 */
547#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
548
549/*
550 * Core HID Setup
551 */
552#define CONFIG_SYS_HID0_INIT 0x000000000
553#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
554 HID0_ENABLE_INSTRUCTION_CACHE | \
555 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
556#define CONFIG_SYS_HID2 HID2_HBE
557
558/*
559 * MMU Setup
560 */
561
562/* DDR: cache cacheable */
563#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
564 BATL_MEMCOHERENCE)
565#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
566 BATU_VS | BATU_VP)
567#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
568#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
569
570/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
571#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
572 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
573#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
574 BATU_VP)
575#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
576#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
577
578/* FLASH: icache cacheable, but dcache-inhibit and guarded */
579#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
580 BATL_MEMCOHERENCE)
581#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
582 BATU_VS | BATU_VP)
583#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
584 BATL_CACHEINHIBIT | \
585 BATL_GUARDEDSTORAGE)
586#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
587
588/* Stack in dcache: cacheable, no memory coherence */
589#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
590#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
591 BATU_VS | BATU_VP)
592#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
593#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
594
595/*
596 * Environment Configuration
597 */
598
599#define CONFIG_ENV_OVERWRITE
600
601#if defined(CONFIG_TSEC_ENET)
602#define CONFIG_HAS_ETH0
603#endif
604
605#define CONFIG_BAUDRATE 115200
606
607#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
608
609#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
610
611#define CONFIG_HOSTNAME hrcon
612#define CONFIG_ROOTPATH "/opt/nfsroot"
613#define CONFIG_BOOTFILE "uImage"
614
615#define CONFIG_PREBOOT /* enable preboot variable */
616
617#define CONFIG_EXTRA_ENV_SETTINGS \
618 "netdev=eth0\0" \
619 "consoledev=ttyS1\0" \
620 "u-boot=u-boot.bin\0" \
621 "kernel_addr=1000000\0" \
622 "fdt_addr=C00000\0" \
623 "fdtfile=hrcon.dtb\0" \
624 "load=tftp ${loadaddr} ${u-boot}\0" \
625 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
626 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
627 " +${filesize};cp.b ${fileaddr} " \
628 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
629 "upd=run load update\0" \
630
631#define CONFIG_NFSBOOTCOMMAND \
632 "setenv bootargs root=/dev/nfs rw " \
633 "nfsroot=$serverip:$rootpath " \
634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "tftp ${kernel_addr} $bootfile;" \
637 "tftp ${fdt_addr} $fdtfile;" \
638 "bootm ${kernel_addr} - ${fdt_addr}"
639
640#define CONFIG_MMCBOOTCOMMAND \
641 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
642 "console=$consoledev,$baudrate $othbootargs;" \
643 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
644 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
645 "bootm ${kernel_addr} - ${fdt_addr}"
646
647#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
648
649
650#endif /* __CONFIG_H */