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Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +02001// SPDX-License-Identifier: GPL-2.0+
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +03002/*
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +02003 * Copyright (C) 2016- 2021 Marvell International Ltd.
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +03004 */
5
6/*
7 * Device Tree file for Marvell Armada 7040 Development board platform
8 * Boot device: NAND, 0xE (SW3)
9 */
10
11#include "armada-7040.dtsi"
12
13/ {
14 model = "Marvell Armada 7040 DB board with NAND";
15 compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
16 "marvell,armada7040", "marvell,armada-ap806-quad",
17 "marvell,armada-ap806";
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 aliases {
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020024 i2c0 = &cp0_i2c0;
25 spi0 = &cp0_spi1;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030026 };
27
28 memory@00000000 {
29 device_type = "memory";
30 reg = <0x0 0x0 0x0 0x80000000>;
31 };
32};
33
34&ap_pinctl {
35 /* MPP Bus:
36 * SDIO [0-5]
37 * UART0 [11,19]
38 */
39 /* 0 1 2 3 4 5 6 7 8 9 */
40 pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
41 0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
42};
43
44&uart0 {
45 status = "okay";
46};
47
48
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020049&cp0_pcie2 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030050 status = "okay";
51};
52
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020053&cp0_i2c0 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030054 pinctrl-names = "default";
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020055 pinctrl-0 = <&cp0_i2c0_pins>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030056 status = "okay";
57 clock-frequency = <100000>;
58};
59
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020060&cp0_pinctl {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030061 /* MPP Bus:
62 * AUDIO [0-5]
63 * GBE [6-11]
64 * SS_PWDN [12]
65 * NF_RBn [13]
66 * GPIO [14]
67 * DEV_BUS [15-27]
68 * SATA1 [28]
69 * UART0 [29-30]
70 * MSS_VTT_EN [31]
71 * SMI [32,34]
72 * XSMI [35-36]
73 * I2C [37-38]
74 * RGMII1 [44-55]
75 * SD [56-61]
76 * GPIO [62]
77 */
78 /* 0 1 2 3 4 5 6 7 8 9 */
79 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
80 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
81 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
82 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
83 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
84 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
85 0xe 0xe 0x0>;
86};
87
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020088&cp0_spi1 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030089 pinctrl-names = "default";
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020090 pinctrl-0 = <&cp0_spi0_pins>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +030091 status = "disabled";
92
93 spi-flash@0 {
94 #address-cells = <0x1>;
95 #size-cells = <0x1>;
96 compatible = "jedec,spi-nor";
97 reg = <0x0>;
98 spi-max-frequency = <20000000>;
99
100 partitions {
101 compatible = "fixed-partitions";
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 partition@0 {
106 label = "U-Boot";
107 reg = <0x0 0x200000>;
108 };
109
110 partition@400000 {
111 label = "Filesystem";
112 reg = <0x200000 0xe00000>;
113 };
114 };
115 };
116};
117
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200118&cp0_sata0 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300119 status = "okay";
120};
121
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200122&cp0_usb3_0 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300123 status = "okay";
124};
125
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200126&cp0_usb3_1 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300127 status = "okay";
128};
129
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200130&cp0_comphy {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300131 phy0 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300132 phy-type = <COMPHY_TYPE_SGMII2>;
133 phy-speed = <COMPHY_SPEED_3_125G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300134 };
135
136 phy1 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300137 phy-type = <COMPHY_TYPE_USB3_HOST0>;
138 phy-speed = <COMPHY_SPEED_5G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300139 };
140
141 phy2 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300142 phy-type = <COMPHY_TYPE_SGMII0>;
143 phy-speed = <COMPHY_SPEED_1_25G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300144 };
145
146 phy3 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300147 phy-type = <COMPHY_TYPE_SATA1>;
148 phy-speed = <COMPHY_SPEED_5G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300149 };
150
151 phy4 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300152 phy-type = <COMPHY_TYPE_USB3_HOST1>;
153 phy-speed = <COMPHY_SPEED_5G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300154 };
155
156 phy5 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300157 phy-type = <COMPHY_TYPE_PEX2>;
158 phy-speed = <COMPHY_SPEED_5G>;
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300159 };
160};
161
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200162&cp0_nand {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300163 status = "okay";
164};
165
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200166&cp0_utmi0 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300167 status = "okay";
168};
169
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200170&cp0_utmi1 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300171 status = "okay";
172};
173
174&ap_sdhci0 {
175 status = "okay";
176 bus-width = <4>;
177 no-1-8-v;
178 non-removable;
179};
180
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200181&cp0_sdhci0 {
Konstantin Porotchkin50eacd82017-04-05 18:22:32 +0300182 status = "okay";
183 bus-width = <4>;
184 no-1-8-v;
185 non-removable;
186};