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Chris Brandtba932bc2017-08-23 14:53:59 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the GR-Peach board
4 *
5 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics
7 */
8
9/dts-v1/;
10#include "r7s72100.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13
14/ {
15 model = "GR-Peach";
16 compatible = "renesas,gr-peach", "renesas,r7s72100";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
23 bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@20000000 {
28 device_type = "memory";
29 reg = <0x20000000 0x00a00000>;
30 };
31
32 lbsc {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 };
36
37 flash@18000000 {
38 compatible = "mtd-rom";
39 probe-type = "map_rom";
40 reg = <0x18000000 0x00800000>;
41 bank-width = <4>;
42 device-width = <1>;
43
44 #address-cells = <1>;
45 #size-cells = <1>;
46
47 rootfs@600000 {
48 label = "rootfs";
49 reg = <0x00600000 0x00200000>;
50 };
51 };
52
53 leds {
54 status = "okay";
55 compatible = "gpio-leds";
56
57 led1 {
58 gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
59 };
60 };
61};
62
63&pinctrl {
64 scif2_pins: serial2 {
65 /* P6_2 as RxD2; P6_3 as TxD2 */
66 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
67 };
68
69 ether_pins: ether {
70 /* Ethernet on Ports 1,3,5,10 */
71 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
72 <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
73 <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
74 <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
75 <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
76 <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
77 <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
78 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
79 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
80 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
81 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
82 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
83 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
84 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
85 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
86 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
87 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
88 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
89 };
90};
91
92&extal_clk {
93 clock-frequency = <13333000>;
94};
95
96&usb_x1_clk {
97 clock-frequency = <48000000>;
98};
99
100&mtu2 {
101 status = "okay";
102};
103
104&ostm0 {
105 status = "okay";
106};
107
108&ostm1 {
109 status = "okay";
110};
111
112&scif2 {
113 pinctrl-names = "default";
114 pinctrl-0 = <&scif2_pins>;
115
116 status = "okay";
117};
118
119&ether {
120 pinctrl-names = "default";
121 pinctrl-0 = <&ether_pins>;
122
123 status = "okay";
124
125 renesas,no-ether-link;
126 phy-handle = <&phy0>;
127
128 phy0: ethernet-phy@0 {
129 reg = <0>;
130
131 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
132 reset-delay-us = <5>;
133 };
134};