blob: 425ad0868f8950438b63e71de6db0f64f1649432 [file] [log] [blame]
Stefan Roesec157d8e2005-08-01 16:41:48 +02001/*
2*
3* See file CREDITS for list of people who contributed to this
4* project.
5*
6* This program is free software; you can redistribute it and/or
7* modify it under the terms of the GNU General Public License as
8* published by the Free Software Foundation; either version 2 of
9* the License, or (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19* MA 02111-1307 USA
20*/
21
22#include <ppc_asm.tmpl>
23#include <config.h>
24
25/* General */
26#define TLB_VALID 0x00000200
27
28/* Supported page sizes */
29
30#define SZ_1K 0x00000000
31#define SZ_4K 0x00000010
32#define SZ_16K 0x00000020
33#define SZ_64K 0x00000030
34#define SZ_256K 0x00000040
35#define SZ_1M 0x00000050
36#define SZ_8M 0x00000060
37#define SZ_16M 0x00000070
38#define SZ_256M 0x00000090
39
40/* Storage attributes */
41#define SA_W 0x00000800 /* Write-through */
42#define SA_I 0x00000400 /* Caching inhibited */
43#define SA_M 0x00000200 /* Memory coherence */
44#define SA_G 0x00000100 /* Guarded */
45#define SA_E 0x00000080 /* Endian */
46
47/* Access control */
48#define AC_X 0x00000024 /* Execute */
49#define AC_W 0x00000012 /* Write */
50#define AC_R 0x00000009 /* Read */
51
52/* Some handy macros */
53
54#define EPN(e) ((e) & 0xfffffc00)
55#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
56#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
57#define TLB2(a) ( (a)&0x00000fbf )
58
59#define tlbtab_start\
60 mflr r1 ;\
61 bl 0f ;
62
63#define tlbtab_end\
64 .long 0, 0, 0 ; \
650: mflr r0 ; \
66 mtlr r1 ; \
67 blr ;
68
69#define tlbentry(epn,sz,rpn,erpn,attr)\
70 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
71
72
73/**************************************************************************
74 * TLB TABLE
75 *
76 * This table is used by the cpu boot code to setup the initial tlb
77 * entries. Rather than make broad assumptions in the cpu source tree,
78 * this table lets each board set things up however they like.
79 *
80 * Pointer to the table is returned in r1
81 *
82 *************************************************************************/
83
84 .section .bootpg,"ax"
85 .globl tlbtab
86
87tlbtab:
88 tlbtab_start
Stefan Roese84286382005-08-11 18:03:14 +020089
90 /*
91 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
92 * speed up boot process. It is patched after relocation to enable SA_I
93 */
94 tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
95
96 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
97 tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
98
99 tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
100 tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
101 tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
Stefan Roesec157d8e2005-08-01 16:41:48 +0200102
103 /* PCI */
104 tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
105 tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
106 tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
107 tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
108
109 /* USB 2.0 Device */
110 tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
111
112 tlbtab_end