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wdenka8bd82d2004-04-18 22:03:42 +00001/*
2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from r8169.c of etherboot
7 *
8 */
9
10/**************************************************************************
11* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12* Written 2003 by Timothy Legge <tlegge@rogers.com>
13*
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
wdenka8bd82d2004-04-18 22:03:42 +000015*
16* Portions of this code based on:
17* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18* for Linux kernel 2.4.x.
19*
20* Written 2002 ShuChen <shuchen@realtek.com.tw>
21* See Linux Driver for full information
22*
23* Linux Driver Version 1.27a, 10.02.2002
24*
25* Thanks to:
26* Jean Chen of RealTek Semiconductor Corp. for
27* providing the evaluation NIC used to develop
28* this driver. RealTek's support for Etherboot
29* is appreciated.
30*
31* REVISION HISTORY:
32* ================
33*
34* v1.0 11-26-2003 timlegge Initial port of Linux driver
35* v1.5 01-17-2004 timlegge Initial driver output cleanup
36*
37* Indent Options: indent -kr -i8
38***************************************************************************/
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +010039/*
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
42 */
wdenka8bd82d2004-04-18 22:03:42 +000043#include <common.h>
Simon Glassd0a5a0b2015-07-06 16:47:45 -060044#include <dm.h>
Thierry Redingd58acdc2014-12-09 22:25:26 -070045#include <errno.h>
wdenka8bd82d2004-04-18 22:03:42 +000046#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060047#include <memalign.h>
wdenka8bd82d2004-04-18 22:03:42 +000048#include <net.h>
Simon Glassd0a5a0b2015-07-06 16:47:45 -060049#ifndef CONFIG_DM_ETH
Ben Warren02d69892008-08-31 09:49:42 -070050#include <netdev.h>
Simon Glassd0a5a0b2015-07-06 16:47:45 -060051#endif
wdenka8bd82d2004-04-18 22:03:42 +000052#include <asm/io.h>
53#include <pci.h>
54
wdenka8bd82d2004-04-18 22:03:42 +000055#undef DEBUG_RTL8169
56#undef DEBUG_RTL8169_TX
57#undef DEBUG_RTL8169_RX
58
59#define drv_version "v1.5"
60#define drv_date "01-17-2004"
61
Thierry Reding744152f2015-03-20 12:41:21 +010062static unsigned long ioaddr;
wdenka8bd82d2004-04-18 22:03:42 +000063
64/* Condensed operations for readability. */
wdenka8bd82d2004-04-18 22:03:42 +000065#define currticks() get_timer(0)
wdenka8bd82d2004-04-18 22:03:42 +000066
67/* media options */
68#define MAX_UNITS 8
69static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
70
71/* MAC address length*/
72#define MAC_ADDR_LEN 6
73
74/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
75#define MAX_ETH_FRAME_SIZE 1536
76
77#define TX_FIFO_THRESH 256 /* In bytes */
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
84#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85
86#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
Thierry Redingc94bbfd2014-12-09 22:25:24 -070087#ifdef CONFIG_SYS_RX_ETH_BUFFER
88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
89#else
90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
91#endif
wdenka8bd82d2004-04-18 22:03:42 +000092#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define RX_BUF_LEN 8192
94
95#define RTL_MIN_IO_SIZE 0x80
96#define TX_TIMEOUT (6*HZ)
97
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +010098/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
Thierry Reding744152f2015-03-20 12:41:21 +010099#define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb(ioaddr + (reg))
103#define RTL_R16(reg) readw(ioaddr + (reg))
104#define RTL_R32(reg) readl(ioaddr + (reg))
wdenka8bd82d2004-04-18 22:03:42 +0000105
106#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
107#define ETH_ALEN MAC_ADDR_LEN
108#define ETH_ZLEN 60
109
Thierry Reding744152f2015-03-20 12:41:21 +0100110#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
111 (pci_addr_t)(unsigned long)a)
112#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
113 (phys_addr_t)a)
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900114
wdenka8bd82d2004-04-18 22:03:42 +0000115enum RTL8169_registers {
116 MAC0 = 0, /* Ethernet hardware address. */
117 MAR0 = 8, /* Multicast filter. */
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900118 TxDescStartAddrLow = 0x20,
119 TxDescStartAddrHigh = 0x24,
120 TxHDescStartAddrLow = 0x28,
121 TxHDescStartAddrHigh = 0x2c,
wdenka8bd82d2004-04-18 22:03:42 +0000122 FLASH = 0x30,
123 ERSR = 0x36,
124 ChipCmd = 0x37,
125 TxPoll = 0x38,
126 IntrMask = 0x3C,
127 IntrStatus = 0x3E,
128 TxConfig = 0x40,
129 RxConfig = 0x44,
130 RxMissed = 0x4C,
131 Cfg9346 = 0x50,
132 Config0 = 0x51,
133 Config1 = 0x52,
134 Config2 = 0x53,
135 Config3 = 0x54,
136 Config4 = 0x55,
137 Config5 = 0x56,
138 MultiIntr = 0x5C,
139 PHYAR = 0x60,
140 TBICSR = 0x64,
141 TBI_ANAR = 0x68,
142 TBI_LPAR = 0x6A,
143 PHYstatus = 0x6C,
144 RxMaxSize = 0xDA,
145 CPlusCmd = 0xE0,
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900146 RxDescStartAddrLow = 0xE4,
147 RxDescStartAddrHigh = 0xE8,
wdenka8bd82d2004-04-18 22:03:42 +0000148 EarlyTxThres = 0xEC,
149 FuncEvent = 0xF0,
150 FuncEventMask = 0xF4,
151 FuncPresetState = 0xF8,
152 FuncForceEvent = 0xFC,
153};
154
155enum RTL8169_register_content {
156 /*InterruptStatusBits */
157 SYSErr = 0x8000,
158 PCSTimeout = 0x4000,
159 SWInt = 0x0100,
160 TxDescUnavail = 0x80,
161 RxFIFOOver = 0x40,
162 RxUnderrun = 0x20,
163 RxOverflow = 0x10,
164 TxErr = 0x08,
165 TxOK = 0x04,
166 RxErr = 0x02,
167 RxOK = 0x01,
168
169 /*RxStatusDesc */
170 RxRES = 0x00200000,
171 RxCRC = 0x00080000,
172 RxRUNT = 0x00100000,
173 RxRWT = 0x00400000,
174
175 /*ChipCmdBits */
176 CmdReset = 0x10,
177 CmdRxEnb = 0x08,
178 CmdTxEnb = 0x04,
179 RxBufEmpty = 0x01,
180
181 /*Cfg9346Bits */
182 Cfg9346_Lock = 0x00,
183 Cfg9346_Unlock = 0xC0,
184
185 /*rx_mode_bits */
186 AcceptErr = 0x20,
187 AcceptRunt = 0x10,
188 AcceptBroadcast = 0x08,
189 AcceptMulticast = 0x04,
190 AcceptMyPhys = 0x02,
191 AcceptAllPhys = 0x01,
192
193 /*RxConfigBits */
194 RxCfgFIFOShift = 13,
195 RxCfgDMAShift = 8,
196
197 /*TxConfigBits */
198 TxInterFrameGapShift = 24,
199 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
200
201 /*rtl8169_PHYstatus */
202 TBI_Enable = 0x80,
203 TxFlowCtrl = 0x40,
204 RxFlowCtrl = 0x20,
205 _1000bpsF = 0x10,
206 _100bps = 0x08,
207 _10bps = 0x04,
208 LinkStatus = 0x02,
209 FullDup = 0x01,
210
211 /*GIGABIT_PHY_registers */
212 PHY_CTRL_REG = 0,
213 PHY_STAT_REG = 1,
214 PHY_AUTO_NEGO_REG = 4,
215 PHY_1000_CTRL_REG = 9,
216
217 /*GIGABIT_PHY_REG_BIT */
218 PHY_Restart_Auto_Nego = 0x0200,
219 PHY_Enable_Auto_Nego = 0x1000,
220
221 /* PHY_STAT_REG = 1; */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100222 PHY_Auto_Nego_Comp = 0x0020,
wdenka8bd82d2004-04-18 22:03:42 +0000223
224 /* PHY_AUTO_NEGO_REG = 4; */
225 PHY_Cap_10_Half = 0x0020,
226 PHY_Cap_10_Full = 0x0040,
227 PHY_Cap_100_Half = 0x0080,
228 PHY_Cap_100_Full = 0x0100,
229
230 /* PHY_1000_CTRL_REG = 9; */
231 PHY_Cap_1000_Full = 0x0200,
232
233 PHY_Cap_Null = 0x0,
234
235 /*_MediaType*/
236 _10_Half = 0x01,
237 _10_Full = 0x02,
238 _100_Half = 0x04,
239 _100_Full = 0x08,
240 _1000_Full = 0x10,
241
242 /*_TBICSRBit*/
243 TBILinkOK = 0x02000000,
244};
245
246static struct {
247 const char *name;
248 u8 version; /* depend on RTL8169 docs */
249 u32 RxConfigMask; /* should clear the bits supported by this chip */
250} rtl_chip_info[] = {
251 {"RTL-8169", 0x00, 0xff7e1880,},
252 {"RTL-8169", 0x04, 0xff7e1880,},
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900253 {"RTL-8169", 0x00, 0xff7e1880,},
254 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
255 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
256 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
257 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
258 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
259 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
Thierry Reding22872862013-09-20 16:03:43 +0200260 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
Thierry Reding65a66912013-09-20 16:03:44 +0200261 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
Thierry Redingcc0856c2014-12-09 22:25:27 -0700262 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900263 {"RTL-8101e", 0x34, 0xff7e1880,},
264 {"RTL-8100e", 0x32, 0xff7e1880,},
wdenka8bd82d2004-04-18 22:03:42 +0000265};
266
267enum _DescStatusBit {
268 OWNbit = 0x80000000,
269 EORbit = 0x40000000,
270 FSbit = 0x20000000,
271 LSbit = 0x10000000,
272};
273
274struct TxDesc {
275 u32 status;
276 u32 vlan_tag;
277 u32 buf_addr;
278 u32 buf_Haddr;
279};
280
281struct RxDesc {
282 u32 status;
283 u32 vlan_tag;
284 u32 buf_addr;
285 u32 buf_Haddr;
286};
287
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600288static unsigned char rxdata[RX_BUF_LEN];
289
Thierry Redingdad3ba02014-12-09 22:25:25 -0700290#define RTL8169_DESC_SIZE 16
wdenka8bd82d2004-04-18 22:03:42 +0000291
Thierry Redingdad3ba02014-12-09 22:25:25 -0700292#if ARCH_DMA_MINALIGN > 256
293# define RTL8169_ALIGN ARCH_DMA_MINALIGN
294#else
295# define RTL8169_ALIGN 256
296#endif
297
298/*
299 * Warn if the cache-line size is larger than the descriptor size. In such
300 * cases the driver will likely fail because the CPU needs to flush the cache
301 * when requeuing RX buffers, therefore descriptors written by the hardware
302 * may be discarded.
Thierry Redingd58acdc2014-12-09 22:25:26 -0700303 *
304 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
305 * the driver to allocate descriptors from a pool of non-cached memory.
Thierry Redingdad3ba02014-12-09 22:25:25 -0700306 */
307#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600308#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
309 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
Thierry Redingdad3ba02014-12-09 22:25:25 -0700310#warning cache-line size is larger than descriptor size
311#endif
Thierry Redingd58acdc2014-12-09 22:25:26 -0700312#endif
wdenka8bd82d2004-04-18 22:03:42 +0000313
Thierry Redingdad3ba02014-12-09 22:25:25 -0700314/*
315 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
316 * descriptors point to a part of this buffer.
317 */
318DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
319
320/*
321 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
322 * descriptors point to a part of this buffer.
323 */
324DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
wdenka8bd82d2004-04-18 22:03:42 +0000325
326struct rtl8169_private {
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600327 ulong iobase;
wdenka8bd82d2004-04-18 22:03:42 +0000328 void *mmio_addr; /* memory map physical address */
329 int chipset;
330 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
331 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
332 unsigned long dirty_tx;
wdenka8bd82d2004-04-18 22:03:42 +0000333 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
334 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
335 unsigned char *RxBufferRings; /* Index of Rx Buffer */
336 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
337 unsigned char *Tx_skbuff[NUM_TX_DESC];
338} tpx;
339
340static struct rtl8169_private *tpc;
341
342static const u16 rtl8169_intr_mask =
343 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
344 TxOK | RxErr | RxOK;
345static const unsigned int rtl8169_rx_config =
346 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
347
348static struct pci_device_id supported[] = {
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
351 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
wdenka8bd82d2004-04-18 22:03:42 +0000352 {}
353};
354
355void mdio_write(int RegAddr, int value)
356{
357 int i;
358
359 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
360 udelay(1000);
361
362 for (i = 2000; i > 0; i--) {
363 /* Check if the RTL8169 has completed writing to the specified MII register */
364 if (!(RTL_R32(PHYAR) & 0x80000000)) {
365 break;
366 } else {
367 udelay(100);
368 }
369 }
370}
371
372int mdio_read(int RegAddr)
373{
374 int i, value = -1;
375
376 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
377 udelay(1000);
378
379 for (i = 2000; i > 0; i--) {
380 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
381 if (RTL_R32(PHYAR) & 0x80000000) {
382 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
383 break;
384 } else {
385 udelay(100);
386 }
387 }
388 return value;
389}
390
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600391static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
wdenka8bd82d2004-04-18 22:03:42 +0000392{
393 int i;
394 u32 tmp;
395
396#ifdef DEBUG_RTL8169
397 printf ("%s\n", __FUNCTION__);
398#endif
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600399 ioaddr = dev_iobase;
wdenka8bd82d2004-04-18 22:03:42 +0000400
401 /* Soft reset the chip. */
402 RTL_W8(ChipCmd, CmdReset);
403
404 /* Check that the chip has finished the reset. */
405 for (i = 1000; i > 0; i--)
406 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
407 break;
408 else
409 udelay(10);
410
411 /* identify chip attached to board */
412 tmp = RTL_R32(TxConfig);
413 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
414
415 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
416 if (tmp == rtl_chip_info[i].version) {
417 tpc->chipset = i;
418 goto match;
419 }
420 }
421
422 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600423 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
424 name);
Wolfgang Denk06c53be2008-07-10 13:16:09 +0200425 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
wdenka8bd82d2004-04-18 22:03:42 +0000426 tpc->chipset = 0;
427
428match:
429 return 0;
430}
431
Thierry Reding22ece0e2013-09-20 16:03:42 +0200432/*
Thierry Redingd58acdc2014-12-09 22:25:26 -0700433 * TX and RX descriptors are 16 bytes. This causes problems with the cache
434 * maintenance on CPUs where the cache-line size exceeds the size of these
435 * descriptors. What will happen is that when the driver receives a packet
436 * it will be immediately requeued for the hardware to reuse. The CPU will
437 * therefore need to flush the cache-line containing the descriptor, which
438 * will cause all other descriptors in the same cache-line to be flushed
439 * along with it. If one of those descriptors had been written to by the
440 * device those changes (and the associated packet) will be lost.
441 *
442 * To work around this, we make use of non-cached memory if available. If
443 * descriptors are mapped uncached there's no need to manually flush them
444 * or invalidate them.
445 *
446 * Note that this only applies to descriptors. The packet data buffers do
447 * not have the same constraints since they are 1536 bytes large, so they
448 * are unlikely to share cache-lines.
449 */
450static void *rtl_alloc_descs(unsigned int num)
451{
452 size_t size = num * RTL8169_DESC_SIZE;
453
454#ifdef CONFIG_SYS_NONCACHED_MEMORY
455 return (void *)noncached_alloc(size, RTL8169_ALIGN);
456#else
457 return memalign(RTL8169_ALIGN, size);
458#endif
459}
460
461/*
Thierry Reding22ece0e2013-09-20 16:03:42 +0200462 * Cache maintenance functions. These are simple wrappers around the more
463 * general purpose flush_cache() and invalidate_dcache_range() functions.
464 */
465
466static void rtl_inval_rx_desc(struct RxDesc *desc)
467{
Thierry Redingd58acdc2014-12-09 22:25:26 -0700468#ifndef CONFIG_SYS_NONCACHED_MEMORY
Thierry Reding22ece0e2013-09-20 16:03:42 +0200469 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
470 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
471
472 invalidate_dcache_range(start, end);
Thierry Redingd58acdc2014-12-09 22:25:26 -0700473#endif
Thierry Reding22ece0e2013-09-20 16:03:42 +0200474}
475
476static void rtl_flush_rx_desc(struct RxDesc *desc)
477{
Thierry Redingd58acdc2014-12-09 22:25:26 -0700478#ifndef CONFIG_SYS_NONCACHED_MEMORY
Thierry Reding22ece0e2013-09-20 16:03:42 +0200479 flush_cache((unsigned long)desc, sizeof(*desc));
Thierry Redingd58acdc2014-12-09 22:25:26 -0700480#endif
Thierry Reding22ece0e2013-09-20 16:03:42 +0200481}
482
483static void rtl_inval_tx_desc(struct TxDesc *desc)
484{
Thierry Redingd58acdc2014-12-09 22:25:26 -0700485#ifndef CONFIG_SYS_NONCACHED_MEMORY
Thierry Reding22ece0e2013-09-20 16:03:42 +0200486 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
487 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
488
489 invalidate_dcache_range(start, end);
Thierry Redingd58acdc2014-12-09 22:25:26 -0700490#endif
Thierry Reding22ece0e2013-09-20 16:03:42 +0200491}
492
493static void rtl_flush_tx_desc(struct TxDesc *desc)
494{
Thierry Redingd58acdc2014-12-09 22:25:26 -0700495#ifndef CONFIG_SYS_NONCACHED_MEMORY
Thierry Reding22ece0e2013-09-20 16:03:42 +0200496 flush_cache((unsigned long)desc, sizeof(*desc));
Thierry Redingd58acdc2014-12-09 22:25:26 -0700497#endif
Thierry Reding22ece0e2013-09-20 16:03:42 +0200498}
499
500static void rtl_inval_buffer(void *buf, size_t size)
501{
502 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
503 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
504
505 invalidate_dcache_range(start, end);
506}
507
508static void rtl_flush_buffer(void *buf, size_t size)
509{
510 flush_cache((unsigned long)buf, size);
511}
512
wdenka8bd82d2004-04-18 22:03:42 +0000513/**************************************************************************
514RECV - Receive a frame
515***************************************************************************/
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600516static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
517 uchar **packetp)
wdenka8bd82d2004-04-18 22:03:42 +0000518{
519 /* return true if there's an ethernet packet ready to read */
520 /* nic->packet should contain data on return */
521 /* nic->packetlen should contain length of data */
522 int cur_rx;
523 int length = 0;
524
525#ifdef DEBUG_RTL8169_RX
526 printf ("%s\n", __FUNCTION__);
527#endif
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600528 ioaddr = dev_iobase;
wdenka8bd82d2004-04-18 22:03:42 +0000529
530 cur_rx = tpc->cur_rx;
Thierry Reding22ece0e2013-09-20 16:03:42 +0200531
532 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
533
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100534 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
535 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100536 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
537 status) & 0x00001FFF) - 4;
wdenka8bd82d2004-04-18 22:03:42 +0000538
Thierry Reding22ece0e2013-09-20 16:03:42 +0200539 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
wdenka8bd82d2004-04-18 22:03:42 +0000540 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
wdenka8bd82d2004-04-18 22:03:42 +0000541
542 if (cur_rx == NUM_RX_DESC - 1)
543 tpc->RxDescArray[cur_rx].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100544 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000545 else
546 tpc->RxDescArray[cur_rx].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100547 cpu_to_le32(OWNbit + RX_BUF_SIZE);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600548 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
549 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)
550 tpc->RxBufferRing[cur_rx]));
Thierry Reding22ece0e2013-09-20 16:03:42 +0200551 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600552#ifdef CONFIG_DM_ETH
553 *packetp = rxdata;
554#else
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500555 net_process_received_packet(rxdata, length);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600556#endif
wdenka8bd82d2004-04-18 22:03:42 +0000557 } else {
558 puts("Error Rx");
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600559 length = -EIO;
wdenka8bd82d2004-04-18 22:03:42 +0000560 }
561 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
562 tpc->cur_rx = cur_rx;
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600563 return length;
wdenka8bd82d2004-04-18 22:03:42 +0000564
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900565 } else {
566 ushort sts = RTL_R8(IntrStatus);
567 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
568 udelay(100); /* wait */
wdenka8bd82d2004-04-18 22:03:42 +0000569 }
570 tpc->cur_rx = cur_rx;
571 return (0); /* initially as this is called to flush the input */
572}
573
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600574#ifdef CONFIG_DM_ETH
575int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
576{
577 struct rtl8169_private *priv = dev_get_priv(dev);
578
579 return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
580}
581#else
582static int rtl_recv(struct eth_device *dev)
583{
Stephen Warrenf3ba5522015-10-02 17:44:34 -0600584 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
585 dev->iobase, NULL);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600586}
587#endif /* nCONFIG_DM_ETH */
588
wdenka8bd82d2004-04-18 22:03:42 +0000589#define HZ 1000
590/**************************************************************************
591SEND - Transmit a frame
592***************************************************************************/
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600593static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
594 void *packet, int length)
wdenka8bd82d2004-04-18 22:03:42 +0000595{
596 /* send the packet to destination */
597
598 u32 to;
599 u8 *ptxb;
600 int entry = tpc->cur_tx % NUM_TX_DESC;
601 u32 len = length;
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100602 int ret;
wdenka8bd82d2004-04-18 22:03:42 +0000603
604#ifdef DEBUG_RTL8169_TX
605 int stime = currticks();
606 printf ("%s\n", __FUNCTION__);
607 printf("sending %d bytes\n", len);
608#endif
609
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600610 ioaddr = dev_iobase;
wdenka8bd82d2004-04-18 22:03:42 +0000611
612 /* point to the current txb incase multiple tx_rings are used */
613 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
614 memcpy(ptxb, (char *)packet, (int)length);
Thierry Reding22ece0e2013-09-20 16:03:42 +0200615 rtl_flush_buffer(ptxb, length);
wdenka8bd82d2004-04-18 22:03:42 +0000616
617 while (len < ETH_ZLEN)
618 ptxb[len++] = '\0';
619
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900620 tpc->TxDescArray[entry].buf_Haddr = 0;
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600621 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
622 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
wdenka8bd82d2004-04-18 22:03:42 +0000623 if (entry != (NUM_TX_DESC - 1)) {
624 tpc->TxDescArray[entry].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100625 cpu_to_le32((OWNbit | FSbit | LSbit) |
626 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
wdenka8bd82d2004-04-18 22:03:42 +0000627 } else {
628 tpc->TxDescArray[entry].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100629 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
630 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
wdenka8bd82d2004-04-18 22:03:42 +0000631 }
Thierry Reding22ece0e2013-09-20 16:03:42 +0200632 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
wdenka8bd82d2004-04-18 22:03:42 +0000633 RTL_W8(TxPoll, 0x40); /* set polling bit */
634
635 tpc->cur_tx++;
636 to = currticks() + TX_TIMEOUT;
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900637 do {
Thierry Reding22ece0e2013-09-20 16:03:42 +0200638 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900639 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100640 && (currticks() < to)); /* wait */
wdenka8bd82d2004-04-18 22:03:42 +0000641
642 if (currticks() >= to) {
643#ifdef DEBUG_RTL8169_TX
Thierry Reding7a36b9c2013-09-20 16:03:41 +0200644 puts("tx timeout/error\n");
645 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
wdenka8bd82d2004-04-18 22:03:42 +0000646#endif
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100647 ret = 0;
wdenka8bd82d2004-04-18 22:03:42 +0000648 } else {
649#ifdef DEBUG_RTL8169_TX
650 puts("tx done\n");
651#endif
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100652 ret = length;
wdenka8bd82d2004-04-18 22:03:42 +0000653 }
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100654 /* Delay to make net console (nc) work properly */
655 udelay(20);
656 return ret;
wdenka8bd82d2004-04-18 22:03:42 +0000657}
658
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600659#ifdef CONFIG_DM_ETH
660int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
661{
662 struct rtl8169_private *priv = dev_get_priv(dev);
663
664 return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length);
665}
666
667#else
668static int rtl_send(struct eth_device *dev, void *packet, int length)
669{
Stephen Warrenf3ba5522015-10-02 17:44:34 -0600670 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
671 dev->iobase, packet, length);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600672}
673#endif
674
675static void rtl8169_set_rx_mode(void)
wdenka8bd82d2004-04-18 22:03:42 +0000676{
677 u32 mc_filter[2]; /* Multicast hash filter */
678 int rx_mode;
679 u32 tmp = 0;
680
681#ifdef DEBUG_RTL8169
682 printf ("%s\n", __FUNCTION__);
683#endif
684
685 /* IFF_ALLMULTI */
686 /* Too many to filter perfectly -- accept all multicasts. */
687 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
688 mc_filter[1] = mc_filter[0] = 0xffffffff;
689
690 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
691 rtl_chip_info[tpc->chipset].RxConfigMask);
692
693 RTL_W32(RxConfig, tmp);
694 RTL_W32(MAR0 + 0, mc_filter[0]);
695 RTL_W32(MAR0 + 4, mc_filter[1]);
696}
697
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600698static void rtl8169_hw_start(pci_dev_t bdf)
wdenka8bd82d2004-04-18 22:03:42 +0000699{
700 u32 i;
701
702#ifdef DEBUG_RTL8169
703 int stime = currticks();
704 printf ("%s\n", __FUNCTION__);
705#endif
706
707#if 0
708 /* Soft reset the chip. */
709 RTL_W8(ChipCmd, CmdReset);
710
711 /* Check that the chip has finished the reset. */
712 for (i = 1000; i > 0; i--) {
713 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
714 break;
715 else
716 udelay(10);
717 }
718#endif
719
720 RTL_W8(Cfg9346, Cfg9346_Unlock);
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900721
722 /* RTL-8169sb/8110sb or previous version */
723 if (tpc->chipset <= 5)
724 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
725
wdenka8bd82d2004-04-18 22:03:42 +0000726 RTL_W8(EarlyTxThres, EarlyTxThld);
727
728 /* For gigabit rtl8169 */
729 RTL_W16(RxMaxSize, RxPacketMaxSize);
730
731 /* Set Rx Config register */
732 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
733 rtl_chip_info[tpc->chipset].RxConfigMask);
734 RTL_W32(RxConfig, i);
735
736 /* Set DMA burst size and Interframe Gap Time */
737 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
738 (InterFrameGap << TxInterFrameGapShift));
739
740
741 tpc->cur_rx = 0;
742
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600743 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
744 (pci_addr_t)(unsigned long)tpc->TxDescArray));
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900745 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600746 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
747 bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray));
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900748 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
749
750 /* RTL-8169sc/8110sc or later version */
751 if (tpc->chipset > 5)
752 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
753
wdenka8bd82d2004-04-18 22:03:42 +0000754 RTL_W8(Cfg9346, Cfg9346_Lock);
755 udelay(10);
756
757 RTL_W32(RxMissed, 0);
758
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600759 rtl8169_set_rx_mode();
wdenka8bd82d2004-04-18 22:03:42 +0000760
761 /* no early-rx interrupts */
762 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
763
764#ifdef DEBUG_RTL8169
Thierry Reding7a36b9c2013-09-20 16:03:41 +0200765 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
wdenka8bd82d2004-04-18 22:03:42 +0000766#endif
767}
768
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600769static void rtl8169_init_ring(pci_dev_t bdf)
wdenka8bd82d2004-04-18 22:03:42 +0000770{
771 int i;
772
773#ifdef DEBUG_RTL8169
774 int stime = currticks();
775 printf ("%s\n", __FUNCTION__);
776#endif
777
778 tpc->cur_rx = 0;
779 tpc->cur_tx = 0;
780 tpc->dirty_tx = 0;
781 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
782 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
783
784 for (i = 0; i < NUM_TX_DESC; i++) {
785 tpc->Tx_skbuff[i] = &txb[i];
786 }
787
788 for (i = 0; i < NUM_RX_DESC; i++) {
789 if (i == (NUM_RX_DESC - 1))
790 tpc->RxDescArray[i].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100791 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000792 else
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100793 tpc->RxDescArray[i].status =
794 cpu_to_le32(OWNbit + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000795
796 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600797 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
798 bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
Thierry Reding22ece0e2013-09-20 16:03:42 +0200799 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
wdenka8bd82d2004-04-18 22:03:42 +0000800 }
801
802#ifdef DEBUG_RTL8169
Thierry Reding7a36b9c2013-09-20 16:03:41 +0200803 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
wdenka8bd82d2004-04-18 22:03:42 +0000804#endif
805}
806
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600807static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr)
wdenka8bd82d2004-04-18 22:03:42 +0000808{
809 int i;
wdenka8bd82d2004-04-18 22:03:42 +0000810
811#ifdef DEBUG_RTL8169
812 int stime = currticks();
813 printf ("%s\n", __FUNCTION__);
814#endif
815
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600816 rtl8169_init_ring(bdf);
817 rtl8169_hw_start(bdf);
wdenka8bd82d2004-04-18 22:03:42 +0000818 /* Construct a perfect filter frame with the mac address as first match
819 * and broadcast for all others */
820 for (i = 0; i < 192; i++)
821 txb[i] = 0xFF;
822
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600823 txb[0] = enetaddr[0];
824 txb[1] = enetaddr[1];
825 txb[2] = enetaddr[2];
826 txb[3] = enetaddr[3];
827 txb[4] = enetaddr[4];
828 txb[5] = enetaddr[5];
wdenka8bd82d2004-04-18 22:03:42 +0000829
830#ifdef DEBUG_RTL8169
Thierry Reding7a36b9c2013-09-20 16:03:41 +0200831 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
wdenka8bd82d2004-04-18 22:03:42 +0000832#endif
833}
834
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600835#ifdef CONFIG_DM_ETH
836static int rtl8169_eth_start(struct udevice *dev)
837{
838 struct eth_pdata *plat = dev_get_platdata(dev);
839
840 rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr);
841
842 return 0;
843}
844#else
wdenka8bd82d2004-04-18 22:03:42 +0000845/**************************************************************************
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600846RESET - Finish setting up the ethernet interface
wdenka8bd82d2004-04-18 22:03:42 +0000847***************************************************************************/
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600848static int rtl_reset(struct eth_device *dev, bd_t *bis)
849{
Stephen Warrenf3ba5522015-10-02 17:44:34 -0600850 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
851 dev->enetaddr);
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600852
853 return 0;
854}
855#endif /* nCONFIG_DM_ETH */
856
857static void rtl_halt_common(unsigned long dev_iobase)
wdenka8bd82d2004-04-18 22:03:42 +0000858{
859 int i;
860
861#ifdef DEBUG_RTL8169
862 printf ("%s\n", __FUNCTION__);
863#endif
864
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600865 ioaddr = dev_iobase;
wdenka8bd82d2004-04-18 22:03:42 +0000866
867 /* Stop the chip's Tx and Rx DMA processes. */
868 RTL_W8(ChipCmd, 0x00);
869
870 /* Disable interrupts by clearing the interrupt mask. */
871 RTL_W16(IntrMask, 0x0000);
872
873 RTL_W32(RxMissed, 0);
874
wdenka8bd82d2004-04-18 22:03:42 +0000875 for (i = 0; i < NUM_RX_DESC; i++) {
876 tpc->RxBufferRing[i] = NULL;
877 }
878}
879
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600880#ifdef CONFIG_DM_ETH
881void rtl8169_eth_stop(struct udevice *dev)
882{
883 struct rtl8169_private *priv = dev_get_priv(dev);
884
885 rtl_halt_common(priv->iobase);
886}
887#else
888/**************************************************************************
889HALT - Turn off ethernet interface
890***************************************************************************/
891static void rtl_halt(struct eth_device *dev)
892{
893 rtl_halt_common(dev->iobase);
894}
895#endif
896
wdenka8bd82d2004-04-18 22:03:42 +0000897/**************************************************************************
898INIT - Look for an adapter, this routine's visible to the outside
899***************************************************************************/
900
901#define board_found 1
902#define valid_link 0
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600903static int rtl_init(unsigned long dev_ioaddr, const char *name,
904 unsigned char *enetaddr)
wdenka8bd82d2004-04-18 22:03:42 +0000905{
906 static int board_idx = -1;
wdenka8bd82d2004-04-18 22:03:42 +0000907 int i, rc;
908 int option = -1, Cap10_100 = 0, Cap1000 = 0;
909
910#ifdef DEBUG_RTL8169
911 printf ("%s\n", __FUNCTION__);
912#endif
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600913 ioaddr = dev_ioaddr;
wdenka8bd82d2004-04-18 22:03:42 +0000914
915 board_idx++;
916
wdenka8bd82d2004-04-18 22:03:42 +0000917 /* point to private storage */
918 tpc = &tpx;
919
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600920 rc = rtl8169_init_board(ioaddr, name);
wdenka8bd82d2004-04-18 22:03:42 +0000921 if (rc)
922 return rc;
923
924 /* Get MAC address. FIXME: read EEPROM */
925 for (i = 0; i < MAC_ADDR_LEN; i++)
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600926 enetaddr[i] = RTL_R8(MAC0 + i);
wdenka8bd82d2004-04-18 22:03:42 +0000927
928#ifdef DEBUG_RTL8169
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900929 printf("chipset = %d\n", tpc->chipset);
wdenka8bd82d2004-04-18 22:03:42 +0000930 printf("MAC Address");
931 for (i = 0; i < MAC_ADDR_LEN; i++)
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600932 printf(":%02x", enetaddr[i]);
wdenka8bd82d2004-04-18 22:03:42 +0000933 putc('\n');
934#endif
935
936#ifdef DEBUG_RTL8169
937 /* Print out some hardware info */
Simon Glassd0a5a0b2015-07-06 16:47:45 -0600938 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
wdenka8bd82d2004-04-18 22:03:42 +0000939#endif
940
941 /* if TBI is not endbled */
942 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
943 int val = mdio_read(PHY_AUTO_NEGO_REG);
944
945 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
946 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
947 if (option > 0) {
948#ifdef DEBUG_RTL8169
949 printf("%s: Force-mode Enabled.\n", dev->name);
950#endif
951 Cap10_100 = 0, Cap1000 = 0;
952 switch (option) {
953 case _10_Half:
954 Cap10_100 = PHY_Cap_10_Half;
955 Cap1000 = PHY_Cap_Null;
956 break;
957 case _10_Full:
958 Cap10_100 = PHY_Cap_10_Full;
959 Cap1000 = PHY_Cap_Null;
960 break;
961 case _100_Half:
962 Cap10_100 = PHY_Cap_100_Half;
963 Cap1000 = PHY_Cap_Null;
964 break;
965 case _100_Full:
966 Cap10_100 = PHY_Cap_100_Full;
967 Cap1000 = PHY_Cap_Null;
968 break;
969 case _1000_Full:
970 Cap10_100 = PHY_Cap_Null;
971 Cap1000 = PHY_Cap_1000_Full;
972 break;
973 default:
974 break;
975 }
976 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
977 mdio_write(PHY_1000_CTRL_REG, Cap1000);
978 } else {
979#ifdef DEBUG_RTL8169
980 printf("%s: Auto-negotiation Enabled.\n",
981 dev->name);
982#endif
983 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
984 mdio_write(PHY_AUTO_NEGO_REG,
985 PHY_Cap_10_Half | PHY_Cap_10_Full |
986 PHY_Cap_100_Half | PHY_Cap_100_Full |
987 (val & 0x1F));
988
989 /* enable 1000 Full Mode */
990 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
991
992 }
993
994 /* Enable auto-negotiation and restart auto-nigotiation */
995 mdio_write(PHY_CTRL_REG,
996 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
997 udelay(100);
998
999 /* wait for auto-negotiation process */
1000 for (i = 10000; i > 0; i--) {
1001 /* check if auto-negotiation complete */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +01001002 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
wdenka8bd82d2004-04-18 22:03:42 +00001003 udelay(100);
1004 option = RTL_R8(PHYstatus);
1005 if (option & _1000bpsF) {
1006#ifdef DEBUG_RTL8169
1007 printf("%s: 1000Mbps Full-duplex operation.\n",
1008 dev->name);
1009#endif
1010 } else {
1011#ifdef DEBUG_RTL8169
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +01001012 printf("%s: %sMbps %s-duplex operation.\n",
1013 dev->name,
1014 (option & _100bps) ? "100" :
1015 "10",
1016 (option & FullDup) ? "Full" :
1017 "Half");
wdenka8bd82d2004-04-18 22:03:42 +00001018#endif
1019 }
1020 break;
1021 } else {
1022 udelay(100);
1023 }
1024 } /* end for-loop to wait for auto-negotiation process */
1025
1026 } else {
1027 udelay(100);
1028#ifdef DEBUG_RTL8169
1029 printf
1030 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1031 dev->name,
1032 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1033#endif
1034 }
1035
Thierry Redingdad3ba02014-12-09 22:25:25 -07001036
Thierry Redingd58acdc2014-12-09 22:25:26 -07001037 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1038 if (!tpc->RxDescArray)
1039 return -ENOMEM;
1040
1041 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1042 if (!tpc->TxDescArray)
1043 return -ENOMEM;
1044
1045 return 0;
wdenka8bd82d2004-04-18 22:03:42 +00001046}
1047
Simon Glassd0a5a0b2015-07-06 16:47:45 -06001048#ifndef CONFIG_DM_ETH
wdenka8bd82d2004-04-18 22:03:42 +00001049int rtl8169_initialize(bd_t *bis)
1050{
1051 pci_dev_t devno;
1052 int card_number = 0;
1053 struct eth_device *dev;
1054 u32 iobase;
1055 int idx=0;
1056
1057 while(1){
Thierry Reding22872862013-09-20 16:03:43 +02001058 unsigned int region;
1059 u16 device;
Thierry Redingd58acdc2014-12-09 22:25:26 -07001060 int err;
Thierry Reding22872862013-09-20 16:03:43 +02001061
wdenka8bd82d2004-04-18 22:03:42 +00001062 /* Find RTL8169 */
1063 if ((devno = pci_find_devices(supported, idx++)) < 0)
1064 break;
1065
Thierry Reding22872862013-09-20 16:03:43 +02001066 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1067 switch (device) {
1068 case 0x8168:
1069 region = 2;
1070 break;
1071
1072 default:
1073 region = 1;
1074 break;
1075 }
1076
1077 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
wdenka8bd82d2004-04-18 22:03:42 +00001078 iobase &= ~0xf;
1079
1080 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1081
1082 dev = (struct eth_device *)malloc(sizeof *dev);
Nobuhiro Iwamatsuf4eaef72010-10-19 14:03:38 +09001083 if (!dev) {
1084 printf("Can not allocate memory of rtl8169\n");
1085 break;
1086 }
wdenka8bd82d2004-04-18 22:03:42 +00001087
Nobuhiro Iwamatsuf4eaef72010-10-19 14:03:38 +09001088 memset(dev, 0, sizeof(*dev));
wdenka8bd82d2004-04-18 22:03:42 +00001089 sprintf (dev->name, "RTL8169#%d", card_number);
1090
Thierry Reding744152f2015-03-20 12:41:21 +01001091 dev->priv = (void *)(unsigned long)devno;
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +01001092 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
wdenka8bd82d2004-04-18 22:03:42 +00001093
1094 dev->init = rtl_reset;
1095 dev->halt = rtl_halt;
1096 dev->send = rtl_send;
1097 dev->recv = rtl_recv;
1098
Simon Glassd0a5a0b2015-07-06 16:47:45 -06001099 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
Thierry Redingd58acdc2014-12-09 22:25:26 -07001100 if (err < 0) {
1101 printf(pr_fmt("failed to initialize card: %d\n"), err);
1102 free(dev);
1103 continue;
1104 }
wdenka8bd82d2004-04-18 22:03:42 +00001105
Thierry Redingd58acdc2014-12-09 22:25:26 -07001106 eth_register (dev);
wdenka8bd82d2004-04-18 22:03:42 +00001107
1108 card_number++;
1109 }
1110 return card_number;
1111}
Simon Glassd0a5a0b2015-07-06 16:47:45 -06001112#endif
1113
1114#ifdef CONFIG_DM_ETH
1115static int rtl8169_eth_probe(struct udevice *dev)
1116{
1117 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1118 struct rtl8169_private *priv = dev_get_priv(dev);
1119 struct eth_pdata *plat = dev_get_platdata(dev);
1120 u32 iobase;
1121 int region;
1122 int ret;
1123
1124 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1125 switch (pplat->device) {
1126 case 0x8168:
1127 region = 2;
1128 break;
1129 default:
1130 region = 1;
1131 break;
1132 }
1133 pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4,
1134 &iobase);
1135 iobase &= ~0xf;
1136 priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase);
1137
1138 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1139 if (ret < 0) {
1140 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1141 return ret;
1142 }
1143
1144 return 0;
1145}
1146
1147static const struct eth_ops rtl8169_eth_ops = {
1148 .start = rtl8169_eth_start,
1149 .send = rtl8169_eth_send,
1150 .recv = rtl8169_eth_recv,
1151 .stop = rtl8169_eth_stop,
1152};
1153
1154static const struct udevice_id rtl8169_eth_ids[] = {
1155 { .compatible = "realtek,rtl8169" },
1156 { }
1157};
1158
1159U_BOOT_DRIVER(eth_rtl8169) = {
1160 .name = "eth_rtl8169",
1161 .id = UCLASS_ETH,
1162 .of_match = rtl8169_eth_ids,
1163 .probe = rtl8169_eth_probe,
1164 .ops = &rtl8169_eth_ops,
1165 .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1166 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1167};
1168
1169U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1170#endif