blob: 01c4171ca6dfd982a49c385b1e6acbe99bc74d1d [file] [log] [blame]
Stefan Roese5e4b3362005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * cpci5200.c - main board support/init for the esd cpci5200.
29 */
30
31#include <common.h>
32#include <mpc5xxx.h>
33#include <pci.h>
34#include <command.h>
35
36#include "mt46v16m16-75.h"
37
38void init_ata_reset(void);
39
40static void sdram_start(int hi_addr)
41{
42 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
43
44 /* unlock mode register */
45 *(vu_long *) MPC5XXX_SDRAM_CTRL =
46 SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
47 __asm__ volatile ("sync");
48
49 /* precharge all banks */
50 *(vu_long *) MPC5XXX_SDRAM_CTRL =
51 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
52 __asm__ volatile ("sync");
53
54 /* set mode register: extended mode */
55 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
56 __asm__ volatile ("sync");
57
58 /* set mode register: reset DLL */
59 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
60 __asm__ volatile ("sync");
61
62 /* precharge all banks */
63 *(vu_long *) MPC5XXX_SDRAM_CTRL =
64 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
65 __asm__ volatile ("sync");
66
67 /* auto refresh */
68 *(vu_long *) MPC5XXX_SDRAM_CTRL =
69 SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
70 __asm__ volatile ("sync");
71
72 /* set mode register */
73 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
74 __asm__ volatile ("sync");
75
76 /* normal operation */
77 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
78 __asm__ volatile ("sync");
79}
80
81/*
82 * ATTENTION: Although partially referenced initdram does NOT make real use
83 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
84 * is something else than 0x00000000.
85 */
86
87long int initdram(int board_type)
88{
89 ulong dramsize = 0;
90 ulong test1, test2;
91
92 /* setup SDRAM chip selects */
93 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
94 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
95 __asm__ volatile ("sync");
96
97 /* setup config registers */
98 *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
99 *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
100 __asm__ volatile ("sync");
101
102 /* set tap delay */
103 *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
104 __asm__ volatile ("sync");
105
106 /* find RAM size using SDRAM CS0 only */
107 sdram_start(0);
108 test1 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
109 sdram_start(1);
110 test2 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
111
112 if (test1 > test2) {
113 sdram_start(0);
114 dramsize = test1;
115 } else {
116 dramsize = test2;
117 }
118
119 /* memory smaller than 1MB is impossible */
120 if (dramsize < (1 << 20)) {
121 dramsize = 0;
122 }
123
124 /* set SDRAM CS0 size according to the amount of RAM found */
125 if (dramsize > 0) {
126 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
127 0x13 + __builtin_ffs(dramsize >> 20) - 1;
128 /* let SDRAM CS1 start right after CS0 */
129 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
130 } else {
131#if 0
132 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
133 /* let SDRAM CS1 start right after CS0 */
134 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
135#else
136 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
137 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
138 /* let SDRAM CS1 start right after CS0 */
139 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
140#endif
141 }
142
143#if 0
144 /* find RAM size using SDRAM CS1 only */
145 sdram_start(0);
146 get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
147 sdram_start(1);
148 get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
149 sdram_start(0);
150#endif
151 /* set SDRAM CS1 size according to the amount of RAM found */
152
153 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
154
155 init_ata_reset();
156 return (dramsize);
157}
158
159int checkboard(void)
160{
161 puts("Board: esd CPCI5200 (cpci5200)\n");
162 return 0;
163}
164
165void flash_preinit(void)
166{
167 /*
168 * Now, when we are in RAM, enable flash write
169 * access for detection process.
170 * Note that CS_BOOT cannot be cleared when
171 * executing in flash.
172 */
173 *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
174}
175
176void flash_afterinit(ulong size)
177{
178 if (size == 0x02000000) {
179 /* adjust mapping */
180 *(vu_long *) MPC5XXX_BOOTCS_START =
181 *(vu_long *) MPC5XXX_CS0_START =
182 START_REG(CFG_BOOTCS_START | size);
183 *(vu_long *) MPC5XXX_BOOTCS_STOP =
184 *(vu_long *) MPC5XXX_CS0_STOP =
185 STOP_REG(CFG_BOOTCS_START | size, size);
186 }
187}
188
189#ifdef CONFIG_PCI
190static struct pci_controller hose;
191
192extern void pci_mpc5xxx_init(struct pci_controller *);
193
194void pci_init_board(void
195 ) {
196 pci_mpc5xxx_init(&hose);
197}
198#endif
199
200#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
201
202#define GPIO_PSC1_4 0x01000000UL
203
204void init_ide_reset(void)
205{
206 debug("init_ide_reset\n");
207
208 /* Configure PSC1_4 as GPIO output for ATA reset */
209 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
210 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
211}
212
213void ide_set_reset(int idereset)
214{
215 debug("ide_reset(%d)\n", idereset);
216
217 if (idereset) {
218 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
219 } else {
220 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
221 }
222}
223#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
224
225#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
226#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
227#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
228#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
229
230#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
231#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
232#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
233#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
234
235#define GPIO_WU6 0x40000000UL
236#define GPIO_USB0 0x00010000UL
237#define GPIO_USB9 0x08000000UL
238#define GPIO_USB9S 0x00080000UL
239
240void init_ata_reset(void)
241{
242 debug("init_ata_reset\n");
243
244 /* Configure GPIO_WU6 as GPIO output for ATA reset */
245 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
246 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
247 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
248 __asm__ volatile ("sync");
249
250 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
251 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
252 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
253 __asm__ volatile ("sync");
254
255 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
256 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
257 __asm__ volatile ("sync");
258
259 if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
260 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
261 __asm__ volatile ("sync");
262 }
263}
264
265int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
266{
267 unsigned int addr;
268 unsigned int size;
269 int i;
270 volatile unsigned long *ptr;
271
272 addr = simple_strtol(argv[1], NULL, 16);
273 size = simple_strtol(argv[2], NULL, 16);
274
275 printf("\nWriting at addr %08x, size %08x.\n", addr, size);
276
277 while (1) {
278 ptr = (volatile unsigned long *)addr;
279 for (i = 0; i < (size >> 2); i++) {
280 *ptr++ = i;
281 }
282
283 /* Abort if ctrl-c was pressed */
284 if (ctrlc()) {
285 puts("\nAbort\n");
286 return 0;
287 }
288 putc('.');
289 }
290 return 0;
291}
292
293U_BOOT_CMD(writepci, 3, 1, do_writepci,
294 "writepci- Write some data to pcibus\n",
295 "<addr> <size>\n" " - Write some data to pcibus.\n");