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Jens Scharsig77e72732010-02-03 22:48:09 +01001/*
2 * (C) Copyright 2008-2009
3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4 * Jens Scharsig <esw@bus-elektronik.de>
5 *
6 * Configuation settings for the EB+CPUx9K2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef _CONFIG_EB_CPUx9K2_H_
28#define _CONFIG_EB_CPUx9K2_H_
29
30/*--------------------------------------------------------------------------*/
31
32#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
33#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
34#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
35#define USE_920T_MMU 1
36
37#define CONFIG_VERSION_VARIABLE 1
38#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
39
40#include <asm/arch/hardware.h> /* needed for port definitions */
41
42#define CONFIG_MISC_INIT_R
43
44/*--------------------------------------------------------------------------*/
45
46#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
47
48#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
49#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
50#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
51
52
53#define CONFIG_BOOT_RETRY_TIME 30
54#define CONFIG_CMDLINE_EDITING
55
56#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
57#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
58#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
59#define CONFIG_SYS_PBSIZE \
60 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
61
62#define CONFIG_STACKSIZE (32*1024) /* regular stack */
63
64/*
65 * ARM asynchronous clock
66 */
67
68#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
69#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
70#define CONFIG_SYS_HZ 1000
71#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
72
73#define AT91_SLOW_CLOCK 32768 /* slow clock */
74
75#define CONFIG_CMDLINE_TAG 1
76#define CONFIG_SETUP_MEMORY_TAGS 1
77#define CONFIG_INITRD_TAG 1
78
79#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
80/* flash */
81#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
82#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
83
84/* clocks */
85#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
86#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
87#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
88
89/*
90 * Size of malloc() pool
91 */
92
93#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
94#define CONFIG_SYS_GBL_DATA_SIZE 128
95
96/*
97 * sdram
98 */
99
100#define CONFIG_NR_DRAM_BANKS 1
101#define PHYS_SDRAM 0x20000000
102#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
103
104#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
105#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
106 PHYS_SDRAM_SIZE - 0x00400000 - \
107 CONFIG_SYS_MALLOC_LEN)
108
109#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
110#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
111#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
112#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
113#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
114#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
115#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
116#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
117#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
118#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
119#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
120#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
121#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
122
123/*
124 * Command line configuration
125 */
126
127#include <config_cmd_default.h>
128
129#define CONFIG_CMD_BMP
130#define CONFIG_CMD_DATE
131#define CONFIG_CMD_DHCP
132#define CONFIG_CMD_I2C
133#define CONFIG_CMD_JFFS2
134#define CONFIG_CMD_MII
135#define CONFIG_CMD_NAND
136#define CONFIG_CMD_PING
137#define CONFIG_I2C_CMD_NO_FLAT
138#define CONFIG_I2C_CMD_TREE
139
140#define CONFIG_SYS_LONGHELP
141
142/*
143 * Filesystems
144 */
145
146#define CONFIG_JFFS2_NAND 1
147
148#ifndef CONFIG_JFFS2_CMDLINE
149#define CONFIG_JFFS2_DEV "nand0"
150#define CONFIG_JFFS2_PART_OFFSET 0
151#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
152#else
153#define MTDIDS_DEFAULT "nor0=0,nand0=1"
154#define MTDPARTS_DEFAULT "mtdparts=" \
155 "0:" \
156 "384k(U-Boot)," \
157 "128k(Env)," \
158 "128k(Splash)," \
159 "4M(Kernel)," \
160 "-(FS)" \
161 ";" \
162 "1:" \
163 "-(jffs2)"
164#endif /* CONFIG_JFFS2_CMDLINE */
165
166/*
167 * Hardware drivers
168 */
169
170/*
171 * UART/CONSOLE
172 */
173
174#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
175
176#define CONFIG_BAUDRATE 115200
177#define CONFIG_AT91RM9200_USART
178#define CONFIG_DBGU /* define DBGU as console */
179
180/*
181 * network
182 */
183#define CONFIG_NET_MULTI 1
184
185#define CONFIG_NET_RETRY_COUNT 10
186#define CONFIG_RESET_PHY_R 1
187
188#define CONFIG_DRIVER_AT91EMAC 1
189#define CONFIG_DRIVER_AT91EMAC_QUIET 1
190#define CONFIG_SYS_RX_ETH_BUFFER 8
191#define CONFIG_MII 1
192
193/*
194 * BOOTP options
195 */
196#define CONFIG_BOOTP_BOOTFILESIZE
197#define CONFIG_BOOTP_BOOTPATH
198#define CONFIG_BOOTP_GATEWAY
199#define CONFIG_BOOTP_HOSTNAME
200
201/*
202 * I2C-Bus
203 */
204
205#define CONFIG_SYS_I2C_SPEED 50000
206#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
207
208#ifndef CONFIG_HARD_I2C
209#define CONFIG_SOFT_I2C
210
211/* Software I2C driver configuration */
212
213#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
214#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
215
216#define CONFIG_SYS_I2C_INIT_BOARD
217
218#define I2C_INIT i2c_init_board();
219#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
220#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
221#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
222#define I2C_SDA(bit) \
223 if (bit) \
224 writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
225 else \
226 writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
227#define I2C_SCL(bit) \
228 if (bit) \
229 writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
230 else \
231 writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
232
233#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
234
235#endif /* CONFIG_HARD_I2C */
236
237/* I2C-RTC */
238
239#ifdef CONFIG_CMD_DATE
240#define CONFIG_RTC_DS1338
241#define CONFIG_SYS_I2C_RTC_ADDR 0x68
242#endif
243
244/* EEPROM */
245
246#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
247#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
248
249/* FLASH organization */
250
251/* NOR-FLASH */
252
253#define CONFIG_FLASH_CFI_DRIVER 1
254
255#define PHYS_FLASH_1 0x10000000
256#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
257#define CONFIG_SYS_FLASH_CFI 1
258#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
259
260#define CONFIG_SYS_FLASH_PROTECTION 1
261#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
262#define CONFIG_SYS_MAX_FLASH_BANKS 1
263#define CONFIG_SYS_MAX_FLASH_SECT 512
264#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
265#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
266
267/* NAND */
268
269#define CONFIG_SYS_NAND_MAX_CHIPS 1
270#define CONFIG_SYS_MAX_NAND_DEVICE 1
271#define CONFIG_SYS_NAND_BASE 0x40000000
272#define CONFIG_SYS_NAND_DBW_8 1
273
274#define CONFIG_SYS_64BIT_VSPRINTF 1
275
276/* Status LED's */
277
278#define CONFIG_STATUS_LED 1
279#define CONFIG_BOARD_SPECIFIC_LED 1
280
281#define STATUS_LED_BOOT 1
282#define STATUS_LED_ACTIVE 0
283
284#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
285#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
286#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
287#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
288#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
289#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
290
291#define CONFIG_VIDEO 1
292
293/* Options */
294
295#ifdef CONFIG_VIDEO
296
297#define CONFIG_VIDEO_VCXK 1
298
299#define CONFIG_SPLASH_SCREEN 1
300
301#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
302#define CONFIG_SYS_VCXK_BASE 0x30000000
303
304#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
305#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
306#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
307
308#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
309#define CONFIG_SYS_VCXK_ENABLE_PORT piob
310#define CONFIG_SYS_VCXK_ENABLE_DDR oer
311
312#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
313#define CONFIG_SYS_VCXK_REQUEST_PORT piob
314#define CONFIG_SYS_VCXK_REQUEST_DDR oer
315
316#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
317#define CONFIG_SYS_VCXK_INVERT_PORT piob
318#define CONFIG_SYS_VCXK_INVERT_DDR oer
319
320#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
321#define CONFIG_SYS_VCXK_RESET_PORT piob
322#define CONFIG_SYS_VCXK_RESET_DDR oer
323
324#endif /* CONFIG_VIDEO */
325
326/* Environment */
327
328#define CONFIG_BOOTDELAY 5
329
330#define CONFIG_ENV_IS_IN_FLASH 1
331#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
332#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
333
334#define CONFIG_BAUDRATE 115200
335
336#define CONFIG_BOOTCOMMAND "run nfsboot"
337
338#define CONFIG_NFSBOOTCOMMAND \
339 "dhcp $(copy_addr) uImage_cpux9k2;" \
340 "run bootargsdefaults;" \
341 "set bootargs $(bootargs) boot=nfs " \
342 ";echo $(bootargs)" \
343 ";bootm"
344
345#define CONFIG_EXTRA_ENV_SETTINGS \
346 "displaywidth=256\0" \
347 "displayheight=512\0" \
348 "displaybsteps=1023\0" \
349 "ubootaddr=10000000\0" \
350 "splashimage=10080000\0" \
351 "kerneladdr=100A0000\0" \
352 "kernelsize=00400000\0" \
353 "rootfsaddr=104A0000\0" \
354 "copy_addr=21200000\0" \
355 "rootfssize=00B60000\0" \
356 "bootargsdefaults=set bootargs " \
357 "console=ttyS0,115200 " \
358 "video=vcxk_fb:xres:${displaywidth}," \
359 "yres:${displayheight}," \
360 "bres:${displaybsteps} " \
361 "mem=62M " \
362 "panic=10 " \
363 "uboot=\\\"${ver}\\\" " \
364 "\0" \
365 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
366 "dhcp $(copy_addr) uImage_cpux9k2;" \
367 "erase $(kerneladdr) +$(kernelsize);" \
368 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
369 "protect on $(kerneladdr) +$(kernelsize)" \
370 "\0" \
371 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
372 "dhcp $(copy_addr) rfs;" \
373 "erase $(rootfsaddr) +$(rootfssize);" \
374 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
375 "\0" \
376 "update_uboot=protect off 10000000 1005FFFF;" \
377 "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
378 "erase 10000000 1005FFFF;" \
379 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
380 "protect on 10000000 1005FFFF;reset\0" \
381 "update_splash=protect off $(splashimage) +20000;" \
382 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
383 "erase $(splashimage) +20000;" \
384 "cp.b $(fileaddr) 10080000 $(filesize);" \
385 "protect on $(splashimage) +20000;reset\0" \
386 "emergency=run bootargsdefaults;" \
387 "set bootargs $(bootargs) root=initramfs boot=emergency " \
388 ";bootm $(kerneladdr)\0" \
389 "netemergency=run bootargsdefaults;" \
390 "dhcp $(copy_addr) uImage_cpux9k2;" \
391 "set bootargs $(bootargs) root=initramfs boot=emergency " \
392 ";bootm $(copy_addr)\0" \
393 "norboot=run bootargsdefaults;" \
394 "set bootargs $(bootargs) root=initramfs boot=local " \
395 ";bootm $(kerneladdr)\0" \
396 "nandboot=run bootargsdefaults;" \
397 "set bootargs $(bootargs) root=initramfs boot=nand " \
398 ";bootm $(kerneladdr)\0" \
399 "uu=run update_uboot\0" \
400 "ur=run update_root;run nk\0" \
401 "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
402 "boot=local " \
403 ";echo $(bootargs)" \
404 ";dhcp uImage_cpux9k2;bootm\0" \
405 "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
406 "boot=nand " \
407 ";echo $(bootargs)" \
408 ";dhcp uImage_cpux9k2;bootm\0" \
409 " "
410
411/*--------------------------------------------------------------------------*/
412
413#endif
414
415/* EOF */