Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 5075279 | 2009-01-21 17:24:39 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
Stefan Roese | 5075279 | 2009-01-21 17:24:39 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __EBI__ |
| 7 | #define __EBI__ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/io.h> |
| 11 | #include "vct.h" |
| 12 | |
| 13 | #define EXT_DEVICE_CHANNEL_3 (0x30000000) |
| 14 | #define EXT_DEVICE_CHANNEL_2 (0x20000000) |
| 15 | #define EXT_DEVICE_CHANNEL_1 (0x10000000) |
| 16 | #define EXT_CPU_ACCESS_ACTIVE (0x00000001) |
| 17 | #define EXT_DMA_ACCESS_ACTIVE (1 << 14) |
| 18 | #define EXT_CPU_IORDY_SL (0x00000001) |
| 19 | |
| 20 | #define EBI_CPU_WRITE (1 << 31) |
| 21 | #define EBI_CPU_ID_SHIFT (28) |
| 22 | #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) |
| 23 | |
| 24 | /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ |
| 25 | #define ADDR_LATCH_ENABLE 0 |
| 26 | #define ADDR_ACTIVATION 4 |
| 27 | #define CHIP_SELECT_START 8 |
| 28 | #define OUTPUT_ENABLE_START 12 |
| 29 | #define WAIT_TIME 28 |
| 30 | #define READ_DURATION 20 |
| 31 | |
| 32 | /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ |
| 33 | #define OUTPUT_ENABLE_END 0 |
| 34 | #define CHIP_SELECT_END 4 |
| 35 | #define ADDR_DEACTIVATION 8 |
| 36 | #define RECOVER_TIME 12 |
| 37 | #define ACK_TIME 20 |
| 38 | |
| 39 | /* various bits in configuration register EBI_DEV[01]_CONFIG1 */ |
| 40 | #define EBI_EXTERNAL_DATA_8 (1 << 8) |
| 41 | #define EBI_EXT_ADDR_SHIFT (1 << 22) |
| 42 | #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT |
| 43 | #define EBI_CHIP_SELECT_1 0x2 |
| 44 | #define EBI_CHIP_SELECT_2 0x4 |
| 45 | #define EBI_BUSY_EN_RD (1 << 12) |
| 46 | #define DIR_ACCESS_WRITE (1 << 20) |
| 47 | #define DIR_ACCESS_MASK (1 << 20) |
| 48 | |
| 49 | /* various bits in configuration register EBI_DEV[01]_CONFIG2 */ |
| 50 | #define ADDRESS_INCREMENT_ON 0x0 |
| 51 | #define ADDRESS_INCREMENT_OFF 0x100 |
| 52 | #define QUEUE_LENGTH_1 0x40 |
| 53 | #define QUEUE_LENGTH_2 0x80 |
| 54 | #define QUEUE_LENGTH_3 0xC0 |
| 55 | #define QUEUE_LENGTH_4 0 |
| 56 | #define CPU_TRANSFER_SIZE_32 0 |
| 57 | #define CPU_TRANSFER_SIZE_16 0x10 |
| 58 | #define CPU_TRANSFER_SIZE_8 0x20 |
| 59 | #define READ_ENDIANNESS_ABCD 0 |
| 60 | #define READ_ENDIANNESS_DCBA 0x4 |
| 61 | #define READ_ENDIANNESS_BADC 0x8 |
| 62 | #define READ_ENDIANNESS_CDAB 0xC |
| 63 | #define WRITE_ENDIANNESS_ABCD 0 |
| 64 | #define WRITE_ENDIANNESS_DCBA 0x1 |
| 65 | #define WRITE_ENDIANNESS_BADC 0x2 |
| 66 | #define WRITE_ENDIANNESS_CDAB 0x3 |
| 67 | |
| 68 | /* various bits in configuration register EBI_CTRL_SIG_ACTLV */ |
| 69 | #define IORDY_ACTIVELEVEL_HIGH (1 << 14) |
| 70 | #define ALE_ACTIVELEVEL_HIGH (1 << 8) |
| 71 | |
| 72 | /* bits in register EBI_SIG_LEVEL */ |
| 73 | #define IORDY_LEVEL_MASK 1 |
| 74 | |
| 75 | static inline void ebi_wait(void) |
| 76 | { |
| 77 | while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) |
| 78 | ; /* wait */ |
| 79 | } |
| 80 | |
| 81 | #endif |