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Michal Simek917c5782019-03-27 20:14:19 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
Michal Simek31958402021-05-10 14:55:34 +020014#include <dt-bindings/phy/phy.h>
Michal Simek917c5782019-03-27 20:14:19 +010015
16/ {
17 model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
Michal Simek50d92832019-06-28 13:16:10 +020018 compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
Michal Simek917c5782019-03-27 20:14:19 +010019 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
23 gpio0 = &gpio;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci0;
27 mmc1 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &dcc;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = <&eeprom>;
40 /* xlnx,fmc-eeprom = FIXME */
41 };
42
43 memory@0 {
44 device_type = "memory";
Michal Simek5dc8f692019-10-14 10:35:03 +020045 reg = <0x0 0x0 0x0 0x80000000>;
Michal Simek917c5782019-03-27 20:14:19 +010046 };
Michal Simek31958402021-05-10 14:55:34 +020047
48 si5332_1: si5332_1 { /* clk0_sgmii - u142 */
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <33333333>; /* FIXME */
52 };
53
54 si5332_2: si5332_2 { /* clk1_usb - u142 */
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <27000000>;
58 };
Michal Simek917c5782019-03-27 20:14:19 +010059};
60
61&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
62 status = "okay";
63 non-removable;
64 disable-wp;
65 bus-width = <8>;
Michal Simek01a6da12020-07-22 17:42:43 +020066 xlnx,mio-bank = <0>;
Michal Simek917c5782019-03-27 20:14:19 +010067};
68
69&uart0 { /* uart0 MIO38-39 */
70 status = "okay";
71 u-boot,dm-pre-reloc;
72};
73
74&uart1 { /* uart1 MIO40-41 */
75 status = "okay";
76 u-boot,dm-pre-reloc;
77};
78
79&sdhci1 { /* sd1 MIO45-51 cd in place */
80 status = "okay";
81 no-1-8-v;
82 disable-wp;
Michal Simek01a6da12020-07-22 17:42:43 +020083 xlnx,mio-bank = <1>;
Michal Simek917c5782019-03-27 20:14:19 +010084};
85
Michal Simek31958402021-05-10 14:55:34 +020086&psgtr {
87 status = "okay";
88 /* sgmii, usb3 */
89 clocks = <&si5332_1>, <&si5332_2>;
90 clock-names = "ref0", "ref1";
91};
92
Michal Simek917c5782019-03-27 20:14:19 +010093&gem0 {
94 status = "okay";
95 phy-handle = <&phy0>;
96 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
97 is-internal-pcspma;
98 /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
Michal Simek2975a422019-08-08 12:44:22 +020099 phy0: ethernet-phy@0 {
Michal Simek917c5782019-03-27 20:14:19 +0100100 reg = <0>;
101 };
102};
103
104&gpio {
105 status = "okay";
106 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
107 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
108 "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
109 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
110 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
111 "", "", "", "", "", /* 25 - 29 */
112 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
113 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
114 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
115 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
116 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
117 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
118 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
119 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
120 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
121 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
122 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
123 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
124 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
125 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
126 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
127 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
128 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
129 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
130 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
131 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
132 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
133 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
134 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
135 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
136 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
137 "", "", "", "", "", /* 150 - 154 */
138 "", "", "", "", "", /* 155 - 159 */
139 "", "", "", "", "", /* 160 - 164 */
140 "", "", "", "", "", /* 165 - 169 */
141 "", "", "", ""; /* 170 - 174 */
142};
143
144&i2c0 { /* MIO 34-35 - can't stay here */
145 status = "okay";
146 clock-frequency = <400000>;
147 i2c-mux@74 { /* u33 */
148 compatible = "nxp,pca9548";
149 #address-cells = <1>;
150 #size-cells = <0>;
151 reg = <0x74>;
152 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
153 i2c@0 { /* PMBUS1 */
154 #address-cells = <1>;
155 #size-cells = <0>;
156 reg = <0>;
157 /* On connector J98 */
158 reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
159 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
160 reg = <0x7>;
161 regulator-name = "reg_vcc_fmc";
162 regulator-min-microvolt = <1800000>;
163 regulator-max-microvolt = <2600000>;
164 /* enable-gpio = <&gpio0 23 0x4>; optional */
165 };
166 reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
167 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
168 reg = <0x8>;
169 };
170 reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
171 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
172 reg = <0x9>;
173 };
174 reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
175 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
176 reg = <0xa>;
177 };
Nishant Mittal74ef6202019-07-24 14:58:52 +0530178 reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
Nishant Mittalebb28f22019-07-24 14:58:52 +0530179 compatible = "ti,tps53681", "ti,tps53679";
Nishant Mittal74ef6202019-07-24 14:58:52 +0530180 reg = <0x60>;
Michal Simek917c5782019-03-27 20:14:19 +0100181 /* vccint, vcc_io_soc */
182 };
183 };
184 i2c@1 { /* PMBUS1_INA226 */
185 #address-cells = <1>;
186 #size-cells = <0>;
187 reg = <1>;
Michal Simeke0c08232019-10-14 10:27:42 +0200188 /* FIXME check alerts coming to SC */
Michal Simek917c5782019-03-27 20:14:19 +0100189 vcc_fmc: ina226@42 { /* u81 */
190 compatible = "ti,ina226";
191 reg = <0x42>;
192 shunt-resistor = <5000>;
193 };
194 vcc_ram: ina226@43 { /* u82 */
195 compatible = "ti,ina226";
196 reg = <0x43>;
197 shunt-resistor = <5000>;
198 };
199 vcc_pslp: ina226@44 { /* u84 */
200 compatible = "ti,ina226";
201 reg = <0x44>;
202 shunt-resistor = <5000>;
203 };
204 vcc_psfp: ina226@45 { /* u87 */
205 compatible = "ti,ina226";
206 reg = <0x45>;
207 shunt-resistor = <5000>;
208 };
209 };
210 i2c@2 { /* PMBUS2 */
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <2>;
214 /* On connector J104 */
215 reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
216 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
217 reg = <0xd>;
218 };
219 reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
220 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
221 reg = <0xe>;
222 };
223 reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
224 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
225 reg = <0xf>;
226 };
227 reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
228 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
229 reg = <0x10>;
230 };
231 reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
232 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
233 reg = <0x11>;
234 };
235 reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
236 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
237 reg = <0x12>;
238 };
239 reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
240 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
241 reg = <0x13>;
242 };
243 reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
244 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
245 reg = <0x14>;
246 };
247 reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
248 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
249 reg = <0x15>;
250 };
251 reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
252 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
253 reg = <0x16>;
254 };
255 reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
256 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
257 reg = <0x17>;
258 };
259 reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
260 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
261 reg = <0x19>;
262 };
263 reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
264 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
265 reg = <0x1a>;
266 };
267 reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
268 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
269 reg = <0x1b>;
270 };
271 reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
272 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
273 reg = <0x1c>;
274 };
275 reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
276 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
277 reg = <0x1d>;
278 };
279 reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
280 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
281 reg = <0x1e>;
282 };
283 reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
284 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
285 reg = <0x1f>;
286 };
287 };
288 i2c@3 { /* PMBUS2_INA226 */
289 #address-cells = <1>;
290 #size-cells = <0>;
291 reg = <3>;
292 /* FIXME check alerts coming to SC */
293 vccaux: ina226@40 { /* u89 */
294 compatible = "ti,ina226";
295 reg = <0x40>;
296 shunt-resistor = <5000>;
297 };
298 vccaux_fmc: ina226@41 { /* u91 */
299 compatible = "ti,ina226";
300 reg = <0x41>;
301 shunt-resistor = <5000>;
302 };
303 vcco_500: ina226@42 { /* u92 */
304 compatible = "ti,ina226";
305 reg = <0x42>;
306 shunt-resistor = <5000>;
307 };
308 vcco_501: ina226@43 { /* u94 */
309 compatible = "ti,ina226";
310 reg = <0x43>;
311 shunt-resistor = <5000>;
312 };
313 vcco_502: ina226@44 { /* u96 */
314 compatible = "ti,ina226";
315 reg = <0x44>;
316 shunt-resistor = <5000>;
317 };
318 vcco_503: ina226@45 { /* u98 */
319 compatible = "ti,ina226";
320 reg = <0x45>;
321 shunt-resistor = <5000>;
322 };
323 vcc_1v8: ina226@46 { /* u100 */
324 compatible = "ti,ina226";
325 reg = <0x46>;
326 shunt-resistor = <5000>;
327 };
328 vcc_3v3: ina226@47 { /* u103 */
329 compatible = "ti,ina226";
330 reg = <0x47>;
331 shunt-resistor = <5000>;
332 };
333 vcc_1v2_ddr4: ina226@48 { /* u105 */
334 compatible = "ti,ina226";
335 reg = <0x48>;
336 shunt-resistor = <1000>;
337 };
338 vcc1v1_lp4: ina226@49 { /* u107 */
339 compatible = "ti,ina226";
340 reg = <0x49>;
341 shunt-resistor = <5000>;
342 };
343 vadj_fmc: ina226@4a { /* u110 */
344 compatible = "ti,ina226";
345 reg = <0x4a>;
346 shunt-resistor = <5000>;
347 };
348 mgtyavcc: ina226@4b { /* u112 */
349 compatible = "ti,ina226";
350 reg = <0x4b>;
351 shunt-resistor = <1000>;
352 };
353 mgtyavtt: ina226@4c { /* u113 */
354 compatible = "ti,ina226";
355 reg = <0x4c>;
356 shunt-resistor = <1000>;
357 };
358 mgtyvccaux: ina226@4d { /* u116 */
359 compatible = "ti,ina226";
360 reg = <0x4d>;
361 shunt-resistor = <5000>;
362 };
363 vcc_bat: ina226@4e { /* u12 */
364 compatible = "ti,ina226";
365 reg = <0x4e>;
366 shunt-resistor = <10000000>; /* 10 ohm */
367 };
368 };
369 i2c@4 { /* LP_I2C_SM */
370 #address-cells = <1>;
371 #size-cells = <0>;
372 reg = <4>;
373 /* connected to J212G */
374 /* zynqmp sm alert or samtec J212H */
375 };
376 /* 5-7 unused */
377 };
378};
379
380&i2c1 { /* i2c1 MIO 36-37 */
381 status = "okay";
382 clock-frequency = <400000>;
383
384 /* Must be enabled via J242 */
385 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
386 compatible = "atmel,24c02";
387 reg = <0x51>;
388 };
389
390 i2c-mux@74 { /* u35 */
391 compatible = "nxp,pca9548";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0x74>;
395 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
396 dc_i2c: i2c@0 { /* DC_I2C */
397 #address-cells = <1>;
398 #size-cells = <0>;
399 reg = <0>;
400 /* Use for storing information about SC board */
401 eeprom: eeprom@54 { /* u34 - m24128 16kB */
402 compatible = "st,24c128", "atmel,24c128";
403 reg = <0x54>;
404 };
405 si570_ref_clk: clock-generator@5d { /* u32 */
406 #clock-cells = <0>;
407 compatible = "silabs,si570";
408 reg = <0x5d>; /* 570JAC000900DG */
409 temperature-stability = <50>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200410 factory-fout = <33333333>;
Michal Simek917c5782019-03-27 20:14:19 +0100411 clock-frequency = <33333333>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200412 clock-output-names = "ref_clk";
Michal Simeka34a12f2021-03-09 12:43:42 +0100413 silabs,skip-recall;
Michal Simek917c5782019-03-27 20:14:19 +0100414 };
415 /* Connection via Samtec J212D */
416 /* Use for storing information about X-PRC card */
417 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
418 compatible = "atmel,24c02";
419 reg = <0x52>;
420 };
421
422 /* Use for setting up certain features on X-PRC card */
423 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
424 compatible = "nxp,pca9534";
425 reg = <0x22>;
426 gpio-controller; /* IRQ not connected */
427 #gpio-cells = <2>;
428 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
429 "", "", "", "";
430 gtr_sel0 {
431 gpio-hog;
432 gpios = <0 0>;
433 input; /* FIXME add meaning */
434 line-name = "sw4_1";
435 };
436 gtr_sel1 {
437 gpio-hog;
438 gpios = <1 0>;
439 input; /* FIXME add meaning */
440 line-name = "sw4_2";
441 };
442 gtr_sel2 {
443 gpio-hog;
444 gpios = <2 0>;
445 input; /* FIXME add meaning */
446 line-name = "sw4_3";
447 };
448 gtr_sel3 {
449 gpio-hog;
450 gpios = <3 0>;
451 input; /* FIXME add meaning */
452 line-name = "sw4_4";
453 };
454 };
455 };
456 i2c@1 { /* FMCP1_IIC */
457 #address-cells = <1>;
458 #size-cells = <0>;
459 reg = <1>;
460 /* FIXME connection to Samtec J51C */
461 /* expected eeprom 0x50 SE cards */
462 };
463 i2c@2 { /* FMCP2_IIC */
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <2>;
467 /* FIXME connection to Samtec J53C */
468 /* expected eeprom 0x50 SE cards */
469 };
470 i2c@3 { /* DDR4_DIMM1 */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <3>;
474 si570_ddr_dimm1: clock-generator@60 { /* u2 */
475 #clock-cells = <0>;
476 compatible = "silabs,si570";
477 reg = <0x60>; /* 570BAB000299DG */
478 temperature-stability = <50>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200479 factory-fout = <200000000>;
480 clock-frequency = <200000000>;
481 clock-output-names = "si570_ddrdimm1_clk";
Michal Simek917c5782019-03-27 20:14:19 +0100482 };
483 /* 0x50 SPD? */
484 };
485 i2c@4 { /* DDR4_DIMM2 */
486 #address-cells = <1>;
487 #size-cells = <0>;
488 reg = <4>;
489 si570_ddr_dimm2: clock-generator@60 { /* u3 */
490 #clock-cells = <0>;
491 compatible = "silabs,si570";
492 reg = <0x60>; /* 570BAB000299DG */
493 temperature-stability = <50>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200494 factory-fout = <200000000>;
495 clock-frequency = <200000000>;
496 clock-output-names = "si570_ddrdimm2_clk";
Michal Simek917c5782019-03-27 20:14:19 +0100497 };
498 /* 0x50 SPD? */
499 };
500 i2c@5 { /* LPDDR4_SI570_CLK */
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <5>;
504 si570_lpddr4: clock-generator@60 { /* u4 */
505 #clock-cells = <0>;
506 compatible = "silabs,si570";
507 reg = <0x60>; /* 570BAB000299DG */
508 temperature-stability = <50>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200509 factory-fout = <200000000>;
510 clock-frequency = <200000000>;
511 clock-output-names = "si570_lpddr4_clk";
Michal Simek917c5782019-03-27 20:14:19 +0100512 };
513 };
514 i2c@6 { /* HSDP_SI570 */
515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <6>;
518 si570_hsdp: clock-generator@5d { /* u5 */
519 #clock-cells = <0>;
520 compatible = "silabs,si570";
521 reg = <0x5d>; /* 570JAC000900DG */
522 temperature-stability = <50>;
Michal Simekbdd368a2019-06-25 08:55:52 +0200523 factory-fout = <156250000>;
524 clock-frequency = <156250000>;
525 clock-output-names = "si570_hsdp_clk";
Michal Simek917c5782019-03-27 20:14:19 +0100526 };
527 };
528 i2c@7 { /* PCIE_CLK */
529 #address-cells = <1>;
530 #size-cells = <0>;
531 reg = <7>;
532 /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
533 /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
534 /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
535 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */
536 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
537 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
538 reg = <0xd8>;
539 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
540 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
541
542 };
543
544 };
545 };
546};
547
548&usb0 {
549 status = "okay";
550 xlnx,usb-polarity = <0>;
551 xlnx,usb-reset-mode = <0>;
552};
553
554&dwc3_0 {
555 status = "okay";
556 dr_mode = "peripheral";
557 snps,dis_u2_susphy_quirk;
558 snps,dis_u3_susphy_quirk;
559 maximum-speed = "super-speed";
Michal Simek31958402021-05-10 14:55:34 +0200560 phy-names = "usb3-phy";
561 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
Michal Simek917c5782019-03-27 20:14:19 +0100562};
563
564&usb1 {
565 status = "okay";
566 xlnx,usb-polarity = <0>;
567 xlnx,usb-reset-mode = <0>;
568};
569
570&dwc3_1 {
571 /delete-property/ phy-names ;
572 /delete-property/ phys ;
573 dr_mode = "host";
574 maximum-speed = "high-speed";
575 snps,dis_u2_susphy_quirk ;
576 snps,dis_u3_susphy_quirk ;
577 status = "okay";
578};
579
580&xilinx_ams {
581 status = "okay";
582};
583
584&ams_ps {
585 status = "okay";
586};
587
588&ams_pl {
589 status = "okay";
590};