blob: c024d78c18ac8a2bc972019a5e8f364be6774da2 [file] [log] [blame]
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -04001/*
2 * U-boot - Configuration file for IP04 board (having BF532 processor)
3 *
4 * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
5 *
6 * Copyright (c) 2005-2010 Analog Devices Inc.
7 *
8 * (C) Copyright 2000-2004
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#ifndef __CONFIG_IP04_H__
15#define __CONFIG_IP04_H__
16
17#include <asm/config-pre.h>
18
19
20/*
21 * Processor Settings
22 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050023#define CONFIG_BFIN_CPU bf532-0.5
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040024#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
25
26
27/*
28 * Clock Settings
29 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
30 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
31 */
32/* CONFIG_CLKIN_HZ is any value in Hz */
33#define CONFIG_CLKIN_HZ 10000000
34/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
35/* 1 = CLKIN / 2 */
36#define CONFIG_CLKIN_HALF 0
37/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
38/* 1 = bypass PLL */
39#define CONFIG_PLL_BYPASS 0
40/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
41/* Values can range from 0-63 (where 0 means 64) */
42#define CONFIG_VCO_MULT 40
43/* CCLK_DIV controls the core clock divider */
44/* Values can be 1, 2, 4, or 8 ONLY */
45#define CONFIG_CCLK_DIV 1
46/* SCLK_DIV controls the system clock divider */
47/* Values can range from 1-15 */
48#define CONFIG_SCLK_DIV 3
49
50
51/*
52 * Memory Settings
53 */
54#define CONFIG_MEM_ADD_WDTH 10
55#define CONFIG_MEM_SIZE 64
56
57#define CONFIG_EBIU_SDRRC_VAL 0x408
58#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
59
60#define CONFIG_EBIU_AMGCTL_VAL 0xFF
61#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
62#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
63
64#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
65#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
66
67
68/*
69 * Network Settings
70 */
71#define ADI_CMDS_NETWORK 1
72#define CONFIG_NET_MULTI 1
73#define CONFIG_HOSTNAME IP04
74
75#define CONFIG_DRIVER_DM9000 1
76#define CONFIG_DM9000_NO_SROM
77#define CONFIG_DM9000_BASE 0x20100000
78#define DM9000_IO CONFIG_DM9000_BASE
79#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
80
81
82/*
83 * Flash Settings
84 */
85#define CONFIG_ENV_OVERWRITE 1
86#define CONFIG_SYS_NO_FLASH /* we have only NAND */
87
88
89/*
90 * SPI Settings
91 */
92#define CONFIG_BFIN_SPI
93#define CONFIG_ENV_SPI_MAX_HZ 30000000
94#define CONFIG_SF_DEFAULT_SPEED 30000000
95#define CONFIG_SPI_FLASH
96#define CONFIG_SPI_FLASH_STMICRO
97#define CONFIG_SPI_FLASH_WINBOND
98
99
100/*
101 * Env Storage Settings
102 */
103#define CONFIG_ENV_IS_IN_SPI_FLASH
104#define CONFIG_PREBOOT "echo starting from spi flash"
105#define CONFIG_ENV_OFFSET 0x30000
106#define CONFIG_ENV_SIZE 0x10000
107#define CONFIG_ENV_SECT_SIZE 0x10000
108
109
110/*
111 * NAND Settings
112 */
113#define CONFIG_NAND_PLAT
114#define CONFIG_SYS_NAND_BASE 0x20000000
115#define CONFIG_SYS_MAX_NAND_DEVICE 1
116
117#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
118#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400119#define BFIN_NAND_WRITE(addr, cmd) \
120 do { \
121 bfin_write8(addr, cmd); \
122 SSYNC(); \
123 } while (0)
124
125#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
126#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400127#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400128
129
130/*
131 * Misc Settings
132 */
133#define CONFIG_BAUDRATE 115200
134#define CONFIG_MISC_INIT_R /* needed for MAC address */
135#define CONFIG_UART_CONSOLE 0
136
137#undef CONFIG_SHOW_BOOT_PROGRESS
138/* Enable this if bootretry required; currently it's disabled */
139#define CONFIG_BOOT_RETRY_TIME -1
140#define CONFIG_BOOTCOMMAND "run nandboot"
141#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
142
143
144/*
145 * Pull in common ADI header for remaining command/environment setup
146 */
147#include <configs/bfin_adi_common.h>
148
149#endif