blob: 67093dfa31f1a6fcdcc605ec0958b3637a61b593 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00005 */
6
7/*
8 * mpc8555cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
wdenk03f5c552004-10-10 21:21:55 +000013#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* High Level Configuration Options */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050017#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000018
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xfff80000
20
Gabor Juhos842033e2013-05-30 07:06:12 +000021#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050022#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020023#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000024#define CONFIG_ENV_OVERWRITE
wdenk03f5c552004-10-10 21:21:55 +000025
Jon Loeliger25eedb22008-03-19 15:02:07 -050026#define CONFIG_FSL_VIA
Timur Tabie8d18542008-07-18 16:52:23 +020027
wdenk03f5c552004-10-10 21:21:55 +000028#ifndef __ASSEMBLY__
29extern unsigned long get_clock_freq(void);
30#endif
31#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
32
33/*
34 * These can be toggled for performance analysis, otherwise use default.
35 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020036#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000038
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
40#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000041
Timur Tabie46fedf2011-08-04 18:03:41 -050042#define CONFIG_SYS_CCSRBAR 0xe0000000
43#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk03f5c552004-10-10 21:21:55 +000044
Jon Loeliger2b40edb2008-03-18 11:12:42 -050045/* DDR Setup */
Jon Loeliger2b40edb2008-03-18 11:12:42 -050046#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
47#define CONFIG_DDR_SPD
48#undef CONFIG_FSL_DDR_INTERACTIVE
49
50#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
53#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000054
Jon Loeliger2b40edb2008-03-18 11:12:42 -050055#define CONFIG_DIMM_SLOTS_PER_CTLR 1
56#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk03f5c552004-10-10 21:21:55 +000057
Jon Loeliger2b40edb2008-03-18 11:12:42 -050058/* I2C addresses of SPD EEPROMs */
59#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
60
61/* Make sure required options are set */
wdenk03f5c552004-10-10 21:21:55 +000062#ifndef CONFIG_SPD_EEPROM
63#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
64#endif
65
Jon Loeliger7202d432005-07-25 11:13:26 -050066#undef CONFIG_CLOCKS_IN_MHZ
67
wdenk03f5c552004-10-10 21:21:55 +000068/*
Jon Loeliger7202d432005-07-25 11:13:26 -050069 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000070 */
Jon Loeliger7202d432005-07-25 11:13:26 -050071
72/*
73 * FLASH on the Local Bus
74 * Two banks, 8M each, using the CFI driver.
75 * Boot from BR0/OR0 bank at 0xff00_0000
76 * Alternate BR1/OR1 bank at 0xff80_0000
77 *
78 * BR0, BR1:
79 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
80 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
81 * Port Size = 16 bits = BRx[19:20] = 10
82 * Use GPCM = BRx[24:26] = 000
83 * Valid = BRx[31] = 1
84 *
85 * 0 4 8 12 16 20 24 28
86 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
87 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
88 *
89 * OR0, OR1:
90 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
91 * Reserved ORx[17:18] = 11, confusion here?
92 * CSNT = ORx[20] = 1
93 * ACS = half cycle delay = ORx[21:22] = 11
94 * SCY = 6 = ORx[24:27] = 0110
95 * TRLX = use relaxed timing = ORx[29] = 1
96 * EAD = use external address latch delay = OR[31] = 1
97 *
98 * 0 4 8 12 16 20 24 28
99 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
100 */
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_BR0_PRELIM 0xff801001
105#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_OR0_PRELIM 0xff806e65
108#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
111#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
112#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
113#undef CONFIG_SYS_FLASH_CHECKSUM
114#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000116
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200117#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000118
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200119#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI
121#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000122
wdenk03f5c552004-10-10 21:21:55 +0000123/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500124 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
127#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000128
129/*
130 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000132 *
133 * For BR2, need:
134 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
135 * port-size = 32-bits = BR2[19:20] = 11
136 * no parity checking = BR2[21:22] = 00
137 * SDRAM for MSEL = BR2[24:26] = 011
138 * Valid = BR[31] = 1
139 *
140 * 0 4 8 12 16 20 24 28
141 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
142 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000144 * FIXME: the top 17 bits of BR2.
145 */
146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000148
149/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000151 *
152 * For OR2, need:
153 * 64MB mask for AM, OR2[0:7] = 1111 1100
154 * XAM, OR2[17:18] = 11
155 * 9 columns OR2[19-21] = 010
156 * 13 rows OR2[23-25] = 100
157 * EAD set for extra time OR[31] = 1
158 *
159 * 0 4 8 12 16 20 24 28
160 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
161 */
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
166#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
167#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
168#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000169
170/*
wdenk03f5c552004-10-10 21:21:55 +0000171 * Common settings for all Local Bus SDRAM commands.
172 * At run time, either BSMA1516 (for CPU 1.1)
173 * or BSMA1617 (for CPU 1.0) (old)
174 * is OR'ed in too.
175 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500176#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
177 | LSDMR_PRETOACT7 \
178 | LSDMR_ACTTORW7 \
179 | LSDMR_BL8 \
180 | LSDMR_WRC4 \
181 | LSDMR_CL3 \
182 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000183 )
184
185/*
186 * The CADMUS registers are connected to CS3 on CDS.
187 * The new memory map places CADMUS at 0xf8000000.
188 *
189 * For BR3, need:
190 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
191 * port-size = 8-bits = BR[19:20] = 01
192 * no parity checking = BR[21:22] = 00
193 * GPMC for MSEL = BR[24:26] = 000
194 * Valid = BR[31] = 1
195 *
196 * 0 4 8 12 16 20 24 28
197 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
198 *
199 * For OR3, need:
200 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
201 * disable buffer ctrl OR[19] = 0
202 * CSNT OR[20] = 1
203 * ACS OR[21:22] = 11
204 * XACS OR[23] = 1
205 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
206 * SETA OR[28] = 0
207 * TRLX OR[29] = 1
208 * EHTR OR[30] = 1
209 * EAD extra time OR[31] = 1
210 *
211 * 0 4 8 12 16 20 24 28
212 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
213 */
214
Jon Loeliger25eedb22008-03-19 15:02:07 -0500215#define CONFIG_FSL_CADMUS
216
wdenk03f5c552004-10-10 21:21:55 +0000217#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_BR3_PRELIM 0xf8000801
219#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_INIT_RAM_LOCK 1
222#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200223#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000224
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200225#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
229#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000230
231/* Serial Port */
232#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_NS16550_SERIAL
234#define CONFIG_SYS_NS16550_REG_SIZE 1
235#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
241#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000242
Jon Loeliger20476722006-10-20 15:50:15 -0500243/*
244 * I2C
245 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200246#define CONFIG_SYS_I2C
247#define CONFIG_SYS_I2C_FSL
248#define CONFIG_SYS_FSL_I2C_SPEED 400000
249#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
250#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
251#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk03f5c552004-10-10 21:21:55 +0000252
Timur Tabie8d18542008-07-18 16:52:23 +0200253/* EEPROM */
254#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_I2C_EEPROM_CCID
256#define CONFIG_SYS_ID_EEPROM
257#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
258#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200259
wdenk03f5c552004-10-10 21:21:55 +0000260/*
261 * General PCI
262 * Addresses are mapped 1-1.
263 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600264#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600265#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600266#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600268#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600269#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
271#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000272
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600273#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600274#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600275#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600277#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600278#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
280#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000281
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700282#ifdef CONFIG_LEGACY
283#define BRIDGE_ID 17
284#define VIA_ID 2
285#else
286#define BRIDGE_ID 28
287#define VIA_ID 4
288#endif
wdenk03f5c552004-10-10 21:21:55 +0000289
290#if defined(CONFIG_PCI)
291
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500292#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000293
294#undef CONFIG_EEPRO100
295#undef CONFIG_TULIP
296
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500297#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000299
300#endif /* CONFIG_PCI */
301
wdenk03f5c552004-10-10 21:21:55 +0000302#if defined(CONFIG_TSEC_ENET)
303
wdenk03f5c552004-10-10 21:21:55 +0000304#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500305#define CONFIG_TSEC1 1
306#define CONFIG_TSEC1_NAME "TSEC0"
307#define CONFIG_TSEC2 1
308#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000309#define TSEC1_PHY_ADDR 0
310#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000311#define TSEC1_PHYIDX 0
312#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500313#define TSEC1_FLAGS TSEC_GIGABIT
314#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500315
316/* Options are: TSEC[0-1] */
317#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000318
319#endif /* CONFIG_TSEC_ENET */
320
wdenk03f5c552004-10-10 21:21:55 +0000321/*
322 * Environment
323 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200324#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200326#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
327#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000328
329#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000331
Jon Loeliger2835e512007-06-13 13:22:08 -0500332/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500333 * BOOTP options
334 */
335#define CONFIG_BOOTP_BOOTFILESIZE
336#define CONFIG_BOOTP_BOOTPATH
337#define CONFIG_BOOTP_GATEWAY
338#define CONFIG_BOOTP_HOSTNAME
339
Jon Loeliger659e2f62007-07-10 09:10:49 -0500340/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500341 * Command line configuration.
342 */
Kumar Gala1c9aa762008-09-22 23:40:42 -0500343#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500344#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500345
wdenk03f5c552004-10-10 21:21:55 +0000346#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500347 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000348#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500349
wdenk03f5c552004-10-10 21:21:55 +0000350#undef CONFIG_WATCHDOG /* watchdog disabled */
351
352/*
353 * Miscellaneous configurable options
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500356#define CONFIG_CMDLINE_EDITING /* Command-line editing */
357#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500359#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000361#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000363#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
365#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
366#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000367
368/*
369 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500370 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000371 * the maximum mapped by the Linux kernel during initialization.
372 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500373#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
374#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000375
Jon Loeliger2835e512007-06-13 13:22:08 -0500376#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000377#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk03f5c552004-10-10 21:21:55 +0000378#endif
379
wdenk03f5c552004-10-10 21:21:55 +0000380/*
381 * Environment Configuration
382 */
wdenk03f5c552004-10-10 21:21:55 +0000383#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500384#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000385#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000386#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000387#endif
388
389#define CONFIG_IPADDR 192.168.1.253
390
391#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000392#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000393#define CONFIG_BOOTFILE "your.uImage"
wdenk03f5c552004-10-10 21:21:55 +0000394
395#define CONFIG_SERVERIP 192.168.1.1
396#define CONFIG_GATEWAYIP 192.168.1.1
397#define CONFIG_NETMASK 255.255.255.0
398
399#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
400
wdenk03f5c552004-10-10 21:21:55 +0000401#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
402
wdenk03f5c552004-10-10 21:21:55 +0000403#define CONFIG_EXTRA_ENV_SETTINGS \
404 "netdev=eth0\0" \
405 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500406 "ramdiskaddr=600000\0" \
407 "ramdiskfile=your.ramdisk.u-boot\0" \
408 "fdtaddr=400000\0" \
409 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000410
411#define CONFIG_NFSBOOTCOMMAND \
412 "setenv bootargs root=/dev/nfs rw " \
413 "nfsroot=$serverip:$rootpath " \
414 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
415 "console=$consoledev,$baudrate $othbootargs;" \
416 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500417 "tftp $fdtaddr $fdtfile;" \
418 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000419
420#define CONFIG_RAMBOOTCOMMAND \
421 "setenv bootargs root=/dev/ram rw " \
422 "console=$consoledev,$baudrate $othbootargs;" \
423 "tftp $ramdiskaddr $ramdiskfile;" \
424 "tftp $loadaddr $bootfile;" \
425 "bootm $loadaddr $ramdiskaddr"
426
427#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
428
wdenk03f5c552004-10-10 21:21:55 +0000429#endif /* __CONFIG_H */