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Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09001/*
2 * include/configs/alt.h
3 * This file is alt board configuration.
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __ALT_H
11#define __ALT_H
12
13#undef DEBUG
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090014#define CONFIG_R8A7794
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090015#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090016
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090017#include "rcar-gen2-common.h"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090018
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090019#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsuc9b59bf2014-10-31 16:16:28 +090020#define CONFIG_SYS_TEXT_BASE 0x70000000
21#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090022#define CONFIG_SYS_TEXT_BASE 0xE6304000
Nobuhiro Iwamatsuc9b59bf2014-10-31 16:16:28 +090023#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090024
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090025#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsuc9b59bf2014-10-31 16:16:28 +090026#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090028#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
Nobuhiro Iwamatsuc9b59bf2014-10-31 16:16:28 +090029#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090030#define STACK_AREA_SIZE 0xC000
31#define LOW_LEVEL_MERAM_STACK \
32 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
33
34/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090035#define RCAR_GEN2_SDRAM_BASE 0x40000000
36#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
37#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090038
39/* SCIF */
40#define CONFIG_SCIF_CONSOLE
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090041
42/* FLASH */
43#define CONFIG_SPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090044#define CONFIG_SH_QSPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090045#define CONFIG_SPI_FLASH_QUAD
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090046
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090047/* SH Ether */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090048#define CONFIG_SH_ETHER
49#define CONFIG_SH_ETHER_USE_PORT 0
50#define CONFIG_SH_ETHER_PHY_ADDR 0x1
51#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
52#define CONFIG_SH_ETHER_CACHE_WRITEBACK
53#define CONFIG_SH_ETHER_CACHE_INVALIDATE
54#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
55#define CONFIG_PHYLIB
56#define CONFIG_PHY_MICREL
57#define CONFIG_BITBANGMII
58#define CONFIG_BITBANGMII_MULTI
59
60/* Board Clock */
61#define RMOBILE_XTAL_CLK 20000000u
62#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
63#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
64#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
65#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090066
67#define CONFIG_SYS_TMU_CLK_DIV 4
68
69/* i2c */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090070#define CONFIG_SYS_I2C
71#define CONFIG_SYS_I2C_SH
72#define CONFIG_SYS_I2C_SLAVE 0x7F
73#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090074#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090075#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090076#define CONFIG_SYS_I2C_SH_SPEED2 400000
77#define CONFIG_SH_I2C_DATA_HIGH 4
78#define CONFIG_SH_I2C_DATA_LOW 5
79#define CONFIG_SH_I2C_CLOCK 10000000
80
81#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
82
Nobuhiro Iwamatsu7ffc8df2014-10-31 16:30:26 +090083/* USB */
Nobuhiro Iwamatsu7ffc8df2014-10-31 16:30:26 +090084#define CONFIG_USB_EHCI
85#define CONFIG_USB_EHCI_RMOBILE
86#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
87
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090088/* MMCIF */
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090089#define CONFIG_SH_MMCIF
90#define CONFIG_SH_MMCIF_ADDR 0xee200000
91#define CONFIG_SH_MMCIF_CLK 48000000
92
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090093/* Module stop status bits */
94/* INTC-RT */
95#define CONFIG_SMSTP0_ENA 0x00400000
96/* MSIF */
97#define CONFIG_SMSTP2_ENA 0x00002000
98/* INTC-SYS, IRQC */
99#define CONFIG_SMSTP4_ENA 0x00000180
100/* SCIF2 */
101#define CONFIG_SMSTP7_ENA 0x00080000
102
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +0900103/* SDHI */
104#define CONFIG_SH_SDHI_FREQ 97500000
105
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900106#endif /* __ALT_H */