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maxims@google.com0753bc22017-04-17 12:00:21 -07001menu "Watchdog Timer Support"
Ye Li253531b2017-02-22 16:21:48 +08002
Shreenidhi Shedi42537ca2018-02-21 16:50:20 +01003config WATCHDOG
4 bool "Enable U-Boot watchdog reset"
5 help
6 This option enables U-Boot watchdog support where U-Boot is using
7 watchdog_reset function to service watchdog device in U-Boot. Enable
8 this option if you want to service enabled watchdog by U-Boot. Disable
9 this option if you want U-Boot to start watchdog but never service it.
10
Paolo Pisati45a6d232017-02-10 17:28:05 +010011config HW_WATCHDOG
12 bool
13
Xiaoliang Yangda4918a2018-10-18 18:27:46 +080014config WATCHDOG_RESET_DISABLE
15 bool "Disable reset watchdog"
16 help
17 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
18 that the watchdog will not be fed in u-boot.
19
Paolo Pisati45a6d232017-02-10 17:28:05 +010020config BCM2835_WDT
21 bool "Enable BCM2835/2836 watchdog driver"
22 select HW_WATCHDOG
23 help
24 Say Y here to enable the BCM2835/2836 watchdog
25
26 This provides basic infrastructure to support BCM2835/2836 watchdog
27 hardware, with a max timeout of ~15secs.
28
Tom Rini897f7062017-05-12 22:33:24 -040029config OMAP_WATCHDOG
30 bool "TI OMAP watchdog driver"
31 depends on ARCH_OMAP2PLUS
32 select HW_WATCHDOG
33 default y if AM33XX
34 help
35 Say Y here to enable the OMAP3+ watchdog driver.
Felipe Balbi8f8a12d2017-07-05 20:33:20 +030036
37config TANGIER_WATCHDOG
38 bool "Intel Tangier watchdog"
39 depends on INTEL_MID
40 select HW_WATCHDOG
41 help
42 This enables support for watchdog controller available on
43 Intel Tangier SoC. If you're using a board with Intel Tangier
44 SoC, say Y here.
45
Ye Li253531b2017-02-22 16:21:48 +080046config ULP_WATCHDOG
47 bool "i.MX7ULP watchdog"
48 help
49 Say Y here to enable i.MX7ULP watchdog driver.
50
maxims@google.com0753bc22017-04-17 12:00:21 -070051config WDT
52 bool "Enable driver model for watchdog timer drivers"
53 depends on DM
54 help
55 Enable driver model for watchdog timer. At the moment the API
56 is very simple and only supports four operations:
57 start, restart, stop and reset (expire immediately).
58 What exactly happens when the timer expires is up to a particular
59 device/driver.
60
61config WDT_SANDBOX
62 bool "Enable Watchdog Timer support for Sandbox"
63 depends on SANDBOX && WDT
64 help
Michal Simek3b17e192018-03-28 12:57:54 +020065 Enable Watchdog Timer support in Sandbox. This is a dummy device that
66 can be probed and supports all of the methods of WDT, but does not
67 really do anything.
maxims@google.com0753bc22017-04-17 12:00:21 -070068
Marek Behún2b69a672018-04-24 17:21:30 +020069config WDT_ARMADA_37XX
70 bool "Marvell Armada 37xx watchdog timer support"
71 depends on WDT && ARMADA_3700
72 help
73 Enable this to support Watchdog Timer on Marvell Armada 37xx SoC.
74 There are 4 possible clocks which can be used on these SoCs. This
75 driver uses the second clock (ID 1), assuming that so will also
76 Linux's driver.
77
maxims@google.com1eb0a462017-04-17 12:00:22 -070078config WDT_ASPEED
79 bool "Aspeed ast2400/ast2500 watchdog timer support"
80 depends on WDT
81 default y if ARCH_ASPEED
82 help
83 Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
84 The watchdog timer is stopped when initialized. It performs reset, either
85 full SoC reset or CPU or just some peripherals, based on the flags.
86 It currently does not support Boot Flash Addressing Mode Detection or
87 Second Boot.
88
Álvaro Fernández Rojas77331932017-05-16 18:29:09 +020089config WDT_BCM6345
90 bool "BCM6345 watchdog timer support"
Philippe Reynesdcae39e2019-01-31 18:57:37 +010091 depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158)
Álvaro Fernández Rojas77331932017-05-16 18:29:09 +020092 help
93 Select this to enable watchdog timer for BCM6345 SoCs.
94 The watchdog timer is stopped when initialized.
95 It performs full SoC reset.
96
Marek Behún2ab77042017-06-09 19:28:41 +020097config WDT_ORION
98 bool "Orion watchdog timer support"
99 depends on WDT
100 help
101 Select this to enable Orion watchdog timer, which can be found on some
102 Marvell Armada chips.
103
Shreenidhi Shedi42537ca2018-02-21 16:50:20 +0100104config WDT_CDNS
105 bool "Cadence watchdog timer support"
106 depends on WDT
107 imply WATCHDOG
108 help
109 Select this to enable Cadence watchdog timer, which can be found on some
110 Xilinx Microzed Platform.
111
Ryder Lee090543f2018-11-15 10:07:57 +0800112config WDT_MTK
113 bool "MediaTek watchdog timer support"
114 depends on WDT && ARCH_MEDIATEK
115 help
116 Select this to enable watchdog timer for MediaTek SoCs.
117 The watchdog timer is stopped when initialized.
118 It performs full SoC reset.
119
Shreenidhi Shedie0e9caa2018-07-15 02:05:41 +0530120config XILINX_TB_WATCHDOG
121 bool "Xilinx Axi watchdog timer support"
122 depends on WDT
123 imply WATCHDOG
124 help
125 Select this to enable Xilinx Axi watchdog timer, which can be found on some
126 Xilinx Microblaze Platforms.
127
Xiaoliang Yang517066a2018-10-18 17:14:19 +0800128config IMX_WATCHDOG
129 bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
130 select HW_WATCHDOG
131 help
132 Select this to enable the IMX and LSCH2 of Layerscape watchdog
133 driver.
134
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -0700135config WDT_AT91
136 bool "AT91 watchdog timer support"
137 depends on WDT
138 help
139 Select this to enable Microchip watchdog timer, which can be found on
140 some AT91 devices.
141
142config AT91_HW_WDT_TIMEOUT
143 bool "AT91 watchdog timeout specified"
144 depends on WDT_AT91
Stefan Roese053fce82018-10-04 13:39:07 +0200145
146config WDT_MT7621
147 bool "MediaTek MT7621 watchdog timer support"
148 depends on WDT && ARCH_MT7620
149 help
150 Select this to enable Ralink / Mediatek watchdog timer,
151 which can be found on some MediaTek chips.
152
Christophe Leroy749c9aa2018-11-21 08:51:45 +0000153config WDT_MPC8xx
154 bool "MPC8xx watchdog timer support"
155 depends on WDT && MPC8xx
156 select CONFIG_MPC8xx_WATCHDOG
157 help
158 Select this to enable mpc8xx watchdog timer
159
Ye Li253531b2017-02-22 16:21:48 +0800160endmenu