blob: 2ff41e9c1412d5412fabbde679e6ea85651ce43e [file] [log] [blame]
Heiko Schocher7254d922015-05-18 13:32:31 +02001/*
2 * Copyright (C) 2013 Boundary Devices
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6/* ZQ Calibration */
7DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
8DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
9DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
10DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
11DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
12/*
13 * DQS gating, read delay, write delay calibration values
14 */
15DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
16DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
17DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
18DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
19DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
20DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
21DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
22DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
23/* read data bit delay */
24DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
25DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
26DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
27DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
28DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
29DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
30DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
31DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
32/* Complete calibration by forced measurment */
33DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
34DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
35/* in DDR3, 64-bit mode, only MMDC0 is initiated */
36DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
37DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
38DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
39DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
40DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
41DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
42DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
43DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
44DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
45DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
46DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
47
48DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
49DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
50DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
51DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
52DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
53
54/* final ddr setup */
55DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
56DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
57DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
58DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
59DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
60DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000