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Jorge Ramirez-Ortizccaa83f2017-06-26 15:52:47 +02001/*
2 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __DTS_HISTB_CLOCK_H
19#define __DTS_HISTB_CLOCK_H
20
21/* clocks provided by core CRG */
22#define HISTB_OSC_CLK 0
23#define HISTB_APB_CLK 1
24#define HISTB_AHB_CLK 2
Shawn Guo8eef8032019-01-17 12:09:50 +080025#define HISTB_UART1_CLK 3
26#define HISTB_UART2_CLK 4
27#define HISTB_UART3_CLK 5
28#define HISTB_I2C0_CLK 6
29#define HISTB_I2C1_CLK 7
30#define HISTB_I2C2_CLK 8
31#define HISTB_I2C3_CLK 9
32#define HISTB_I2C4_CLK 10
33#define HISTB_I2C5_CLK 11
34#define HISTB_SPI0_CLK 12
35#define HISTB_SPI1_CLK 13
36#define HISTB_SPI2_CLK 14
Jorge Ramirez-Ortizccaa83f2017-06-26 15:52:47 +020037#define HISTB_SCI_CLK 15
38#define HISTB_FMC_CLK 16
39#define HISTB_MMC_BIU_CLK 17
40#define HISTB_MMC_CIU_CLK 18
41#define HISTB_MMC_DRV_CLK 19
42#define HISTB_MMC_SAMPLE_CLK 20
43#define HISTB_SDIO0_BIU_CLK 21
44#define HISTB_SDIO0_CIU_CLK 22
45#define HISTB_SDIO0_DRV_CLK 23
Shawn Guo8eef8032019-01-17 12:09:50 +080046#define HISTB_SDIO0_SAMPLE_CLK 24
Jorge Ramirez-Ortizccaa83f2017-06-26 15:52:47 +020047#define HISTB_PCIE_AUX_CLK 25
48#define HISTB_PCIE_PIPE_CLK 26
49#define HISTB_PCIE_SYS_CLK 27
50#define HISTB_PCIE_BUS_CLK 28
51#define HISTB_ETH0_MAC_CLK 29
52#define HISTB_ETH0_MACIF_CLK 30
53#define HISTB_ETH1_MAC_CLK 31
54#define HISTB_ETH1_MACIF_CLK 32
55#define HISTB_COMBPHY1_CLK 33
Shawn Guo8eef8032019-01-17 12:09:50 +080056#define HISTB_USB2_BUS_CLK 34
57#define HISTB_USB2_PHY_CLK 35
58#define HISTB_USB2_UTMI_CLK 36
59#define HISTB_USB2_12M_CLK 37
60#define HISTB_USB2_48M_CLK 38
61#define HISTB_USB2_OTG_UTMI_CLK 39
62#define HISTB_USB2_PHY1_REF_CLK 40
63#define HISTB_USB2_PHY2_REF_CLK 41
64#define HISTB_COMBPHY0_CLK 42
65#define HISTB_USB3_BUS_CLK 43
66#define HISTB_USB3_UTMI_CLK 44
67#define HISTB_USB3_PIPE_CLK 45
68#define HISTB_USB3_SUSPEND_CLK 46
69#define HISTB_USB3_BUS_CLK1 47
70#define HISTB_USB3_UTMI_CLK1 48
71#define HISTB_USB3_PIPE_CLK1 49
72#define HISTB_USB3_SUSPEND_CLK1 50
Jorge Ramirez-Ortizccaa83f2017-06-26 15:52:47 +020073
74/* clocks provided by mcu CRG */
Shawn Guo8eef8032019-01-17 12:09:50 +080075#define HISTB_MCE_CLK 1
76#define HISTB_IR_CLK 2
77#define HISTB_TIMER01_CLK 3
78#define HISTB_LEDC_CLK 4
79#define HISTB_UART0_CLK 5
80#define HISTB_LSADC_CLK 6
Jorge Ramirez-Ortizccaa83f2017-06-26 15:52:47 +020081
82#endif /* __DTS_HISTB_CLOCK_H */