drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_PCS_V2_H_
#define QCOM_PHY_QMP_PCS_V2_H_

/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_SW_RESET				0x000
#define QPHY_V2_PCS_POWER_DOWN_CONTROL			0x004
#define QPHY_V2_PCS_START_CONTROL			0x008
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0			0x024
#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0			0x028
#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE		0x054
#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL			0x058
#define QPHY_V2_PCS_POWER_STATE_CONFIG1			0x060
#define QPHY_V2_PCS_POWER_STATE_CONFIG2			0x064
#define QPHY_V2_PCS_POWER_STATE_CONFIG4			0x06c
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1			0x080
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2			0x084
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3			0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8
#define QPHY_V2_PCS_FLL_CNTRL1				0x0c0
#define QPHY_V2_PCS_FLL_CNTRL2				0x0c4
#define QPHY_V2_PCS_FLL_CNT_VAL_L			0x0c8
#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL			0x0cc
#define QPHY_V2_PCS_FLL_MAN_CODE			0x0d0
#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL		0x0d4
#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR		0x0d8
#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS		0x178
#define QPHY_V2_PCS_USB_PCS_STATUS			0x17c /* USB */
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB	0x1a8
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS			0x1ac
#define QPHY_V2_PCS_RX_SIGDET_LVL			0x1d8
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB	0x1dc
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1e0

#define QPHY_V2_PCS_PCI_PCS_STATUS			0x174 /* PCI */

#endif