| Bhupesh Sharma | fff404f | 2023-08-14 11:29:25 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef QCOM_PHY_QMP_H_ |
| 7 | #define QCOM_PHY_QMP_H_ |
| 8 | |
| 9 | #include "phy-qcom-qmp-qserdes-com.h" |
| 10 | #include "phy-qcom-qmp-qserdes-txrx.h" |
| 11 | |
| 12 | #include "phy-qcom-qmp-qserdes-com-v3.h" |
| 13 | #include "phy-qcom-qmp-qserdes-txrx-v3.h" |
| 14 | |
| 15 | #include "phy-qcom-qmp-qserdes-pll.h" |
| 16 | |
| 17 | #include "phy-qcom-qmp-pcs-v2.h" |
| 18 | |
| 19 | #include "phy-qcom-qmp-pcs-v3.h" |
| 20 | |
| 21 | /* Only for QMP V3 & V4 PHY - DP COM registers */ |
| 22 | #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 |
| 23 | #define QPHY_V3_DP_COM_SW_RESET 0x04 |
| 24 | #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 |
| 25 | #define QPHY_V3_DP_COM_SWI_CTRL 0x0c |
| 26 | #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 |
| 27 | #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 |
| 28 | #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c |
| 29 | |
| 30 | /* QSERDES V3 COM bits */ |
| 31 | # define QSERDES_V3_COM_BIAS_EN 0x0001 |
| 32 | # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 |
| 33 | # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 |
| 34 | # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 |
| 35 | # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 |
| 36 | # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 |
| 37 | # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 |
| 38 | |
| 39 | /* QSERDES V3 TX bits */ |
| 40 | # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f |
| 41 | # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 |
| 42 | # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f |
| 43 | # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 |
| 44 | |
| 45 | /* QMP PHY - DP PHY registers */ |
| 46 | #define QSERDES_DP_PHY_REVISION_ID0 0x000 |
| 47 | #define QSERDES_DP_PHY_REVISION_ID1 0x004 |
| 48 | #define QSERDES_DP_PHY_REVISION_ID2 0x008 |
| 49 | #define QSERDES_DP_PHY_REVISION_ID3 0x00c |
| 50 | #define QSERDES_DP_PHY_CFG 0x010 |
| 51 | #define QSERDES_DP_PHY_PD_CTL 0x018 |
| 52 | # define DP_PHY_PD_CTL_PWRDN 0x001 |
| 53 | # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 |
| 54 | # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 |
| 55 | # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 |
| 56 | # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 |
| 57 | # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 |
| 58 | # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 |
| 59 | #define QSERDES_DP_PHY_MODE 0x01c |
| 60 | #define QSERDES_DP_PHY_AUX_CFG0 0x020 |
| 61 | #define QSERDES_DP_PHY_AUX_CFG1 0x024 |
| 62 | #define QSERDES_DP_PHY_AUX_CFG2 0x028 |
| 63 | #define QSERDES_DP_PHY_AUX_CFG3 0x02c |
| 64 | #define QSERDES_DP_PHY_AUX_CFG4 0x030 |
| 65 | #define QSERDES_DP_PHY_AUX_CFG5 0x034 |
| 66 | #define QSERDES_DP_PHY_AUX_CFG6 0x038 |
| 67 | #define QSERDES_DP_PHY_AUX_CFG7 0x03c |
| 68 | #define QSERDES_DP_PHY_AUX_CFG8 0x040 |
| 69 | #define QSERDES_DP_PHY_AUX_CFG9 0x044 |
| 70 | |
| 71 | /* Only for QMP V3 PHY - DP PHY registers */ |
| 72 | #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 |
| 73 | # define PHY_AUX_STOP_ERR_MASK 0x01 |
| 74 | # define PHY_AUX_DEC_ERR_MASK 0x02 |
| 75 | # define PHY_AUX_SYNC_ERR_MASK 0x04 |
| 76 | # define PHY_AUX_ALIGN_ERR_MASK 0x08 |
| 77 | # define PHY_AUX_REQ_ERR_MASK 0x10 |
| 78 | |
| 79 | #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c |
| 80 | #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 |
| 81 | |
| 82 | #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 |
| 83 | #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c |
| 84 | #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 |
| 85 | |
| 86 | #define QSERDES_V3_DP_PHY_SPARE0 0x0ac |
| 87 | #define DP_PHY_SPARE0_MASK 0x0f |
| 88 | #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) |
| 89 | |
| 90 | #define QSERDES_V3_DP_PHY_STATUS 0x0c0 |
| 91 | |
| 92 | /* Only for QMP V4 PHY - DP PHY registers */ |
| 93 | #define QSERDES_V4_DP_PHY_CFG_1 0x014 |
| 94 | #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 |
| 95 | #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 |
| 96 | #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 |
| 97 | #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 |
| 98 | #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c |
| 99 | #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 |
| 100 | #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 |
| 101 | #define QSERDES_V4_DP_PHY_STATUS 0x0dc |
| 102 | |
| 103 | /* Only for QMP V4 PHY - PCS_MISC registers */ |
| 104 | #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 |
| 105 | #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 |
| 106 | #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 |
| 107 | #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c |
| 108 | #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 |
| 109 | #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 |
| 110 | |
| 111 | /* Only for QMP V6 PHY - DP PHY registers */ |
| 112 | #define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0 |
| 113 | #define QSERDES_V6_DP_PHY_STATUS 0x0e4 |
| 114 | |
| 115 | #endif |