blob: e74b1bb85ba7bae503783db32f11615f2c85f791 [file] [log] [blame]
wdenkf7d15722004-12-18 22:35:43 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf7d15722004-12-18 22:35:43 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1
37#define CONFIG_MPC860T 1
38#define CONFIG_MPC862 1 /* enable 862 since the */
39#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
40
41#define CONFIG_UC100 1 /* ...on a UC100 module */
42
43#define MPC8XX_FACT 4 /* Multiply by 4 */
44#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
45#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
46 /* define if cant' use get_gclk_freq */
47
48#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49#undef CONFIG_8xx_CONS_SMC2
50#undef CONFIG_8xx_CONS_NONE
51
52#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
53
54#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55
56#define CONFIG_BOOTCOUNT_LIMIT
57
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59
60#define CONFIG_BOARD_TYPES 1 /* support board types */
61
62#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010063 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf7d15722004-12-18 22:35:43 +000064 "echo"
65
66#undef CONFIG_BOOTARGS
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "netdev=eth0\0" \
70 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf7d15722004-12-18 22:35:43 +000072 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "addip=setenv bootargs ${bootargs} " \
74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
75 ":${hostname}:${netdev}:off panic=1\0" \
76 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
wdenkf7d15722004-12-18 22:35:43 +000077 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "bootm ${kernel_addr}\0" \
wdenkf7d15722004-12-18 22:35:43 +000079 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010080 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
wdenkf7d15722004-12-18 22:35:43 +000082 "bootm\0" \
83 "rootpath=/opt/eldk/ppc_8xx\0" \
84 "bootfile=/tftpboot/uc100/uImage\0" \
85 "kernel_addr=40000000\0" \
86 "ramdisk_addr=40100000\0" \
87 "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
88 "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010089 "cp.b 100000 40700000 ${filesize};" \
wdenkf7d15722004-12-18 22:35:43 +000090 "setenv filesize;saveenv\0" \
91 ""
92#define CONFIG_BOOTCOMMAND "run flash_self"
93
94#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
96
97#undef CONFIG_WATCHDOG /* watchdog disabled */
98
99#undef CONFIG_STATUS_LED /* no status-led */
100
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500101/*
102 * BOOTP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_BOOTFILESIZE
109
wdenkf7d15722004-12-18 22:35:43 +0000110
111#define CONFIG_MAC_PARTITION
112#define CONFIG_DOS_PARTITION
113
114#undef CONFIG_RTC_MPC8xx
115#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
116#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
117
118/*
119 * Power On Self Test support
120 */
121#define CONFIG_POST ( CFG_POST_CACHE | \
122 CFG_POST_MEMORY | \
123 CFG_POST_CPU | \
124 CFG_POST_UART | \
125 CFG_POST_SPR )
126#undef CONFIG_POST
127
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500128
129/*
130 * Command line configuration.
131 */
132#include <config_cmd_default.h>
133
134#define CONFIG_CMD_ASKENV
135#define CONFIG_CMD_DATE
136#define CONFIG_CMD_DHCP
137#define CONFIG_CMD_EEPROM
138#define CONFIG_CMD_ELF
139#define CONFIG_CMD_FAT
140#define CONFIG_CMD_I2C
141#define CONFIG_CMD_IDE
142#define CONFIG_CMD_MII
143#define CONFIG_CMD_NFS
144#define CONFIG_CMD_PING
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500145#define CONFIG_CMD_SNTP
146
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500147#ifdef CONFIG_POST
148#define CONFIG_CMD_DIAG
149#endif
150
wdenkf7d15722004-12-18 22:35:43 +0000151
152#define CONFIG_NETCONSOLE
153
wdenkf7d15722004-12-18 22:35:43 +0000154/*
155 * Miscellaneous configurable options
156 */
157#define CFG_LONGHELP /* undef to save memory */
158#define CFG_PROMPT "=> " /* Monitor Command Prompt */
159
160#if 0
161#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
162#endif
163#ifdef CFG_HUSH_PARSER
164#define CFG_PROMPT_HUSH_PS2 "> "
165#endif
166
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500167#if defined(CONFIG_CMD_KGDB)
wdenkf7d15722004-12-18 22:35:43 +0000168#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
169#else
170#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
171#endif
172#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
173#define CFG_MAXARGS 16 /* max number of command args */
174#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
175
176#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
177#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
178
179#define CFG_LOAD_ADDR 0x100000 /* default load address */
180
181#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
182
183#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
184
185#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
186
187/*
188 * Low Level Configuration Settings
189 * (address mappings, register initial values, etc.)
190 * You should know what you are doing if you make changes here.
191 */
192/*-----------------------------------------------------------------------
193 * Internal Memory Mapped Register
194 */
195#define CFG_IMMR 0xF0000000
196
197/*-----------------------------------------------------------------------
198 * Definitions for initial stack pointer and data area (in DPRAM)
199 */
200#define CFG_INIT_RAM_ADDR CFG_IMMR
201#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
202#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
203#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
204#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
205
206/*-----------------------------------------------------------------------
207 * Start addresses for the final memory configuration
208 * (Set up by the startup code)
209 * Please note that CFG_SDRAM_BASE _must_ start at 0
210 */
211#define CFG_SDRAM_BASE 0x00000000
212#define CFG_FLASH_BASE 0x40000000
213#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
214#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
215#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
216
217/*-----------------------------------------------------------------------
218 * Address accessed to reset the board - must not be mapped/assigned
219 */
220#define CFG_RESET_ADDRESS 0x90000000
221
222/*
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
226 */
227#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
228
229/*-----------------------------------------------------------------------
230 * FLASH organization
231 */
232#define CFG_FLASH_CFI /* The flash is CFI compatible */
233#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
234#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
235
236#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
237#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
238
239#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
240#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
241
242#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
243
244#define CFG_ENV_IS_IN_FLASH 1
245#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200246#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
wdenkf7d15722004-12-18 22:35:43 +0000247#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
248
249/* Address and size of Redundant Environment Sector */
250#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
251#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
252
253/*-----------------------------------------------------------------------
254 * Cache Configuration
255 */
256#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500257#if defined(CONFIG_CMD_KGDB)
wdenkf7d15722004-12-18 22:35:43 +0000258#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
259#endif
260
261/*-----------------------------------------------------------------------
262 * SYPCR - System Protection Control 11-9
263 * SYPCR can only be written once after reset!
264 *-----------------------------------------------------------------------
265 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
266 */
267#if defined(CONFIG_WATCHDOG)
268#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
269 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
270#else
271#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
272#endif
273
274/*-----------------------------------------------------------------------
275 * SIUMCR - SIU Module Configuration 11-6
276 *-----------------------------------------------------------------------
277 * PCMCIA config., multi-function pin tri-state
278 */
279#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
280
281/*-----------------------------------------------------------------------
282 * TBSCR - Time Base Status and Control 11-26
283 *-----------------------------------------------------------------------
284 * Clear Reference Interrupt Status, Timebase freezing enabled
285 */
286#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
287
288/*-----------------------------------------------------------------------
289 * RTCSC - Real-Time Clock Status and Control Register 11-27
290 *-----------------------------------------------------------------------
291 */
292#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
293
294/*-----------------------------------------------------------------------
295 * PISCR - Periodic Interrupt Status and Control 11-31
296 *-----------------------------------------------------------------------
297 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 */
299#define CFG_PISCR (PISCR_PS | PISCR_PITF)
300
301/*-----------------------------------------------------------------------
302 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
303 *-----------------------------------------------------------------------
304 * Reset PLL lock status sticky bit, timer expired status bit and timer
305 * interrupt status bit
306 */
307#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
308 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
309
310/*-----------------------------------------------------------------------
311 * SCCR - System Clock and reset Control Register 15-27
312 *-----------------------------------------------------------------------
313 * Set clock output, timebase and RTC source and divider,
314 * power management and some other internal clocks
315 */
316#define SCCR_MASK 0x00000000
317#define CFG_SCCR (SCCR_EBDF11)
318
319/*-----------------------------------------------------------------------
320 * PCMCIA stuff
321 *-----------------------------------------------------------------------
322 *
323 */
324#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
325#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
326#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
327#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
328#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
329#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
330#define CFG_PCMCIA_IO_ADDR (0xEC000000)
331#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
332
333/*-----------------------------------------------------------------------
334 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
335 *-----------------------------------------------------------------------
336 */
337
338#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
339
340#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
341#undef CONFIG_IDE_LED /* LED for ide not supported */
342#undef CONFIG_IDE_RESET /* reset for ide not supported */
343
344#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
345#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
346
347#define CFG_ATA_IDE0_OFFSET 0x0000
348
349#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
350
351/* Offset for data I/O */
352#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
353
354/* Offset for normal register accesses */
355#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
356
357/* Offset for alternate registers */
358#define CFG_ATA_ALT_OFFSET 0x0100
359
360/*-----------------------------------------------------------------------
361 *
362 *-----------------------------------------------------------------------
363 *
364 */
365#define CFG_DER 0
366
367/*
368 * Init Memory Controller:
369 *
370 * BR0/1 and OR0/1 (FLASH)
371 */
372
373#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
374#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
375
376/* used to re-map FLASH both when starting from SRAM or FLASH:
377 * restrict access enough to keep SRAM working (if any)
378 * but not too much to meddle with FLASH accesses
379 */
380#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
381#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
382
383/*
384 * FLASH timing:
385 */
386#define CFG_OR_TIMING_FLASH (0x00000d24)
387
388#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
389#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
390#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
391
392#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
393#define CFG_OR1_PRELIM 0xfc000a00
394#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
395#define CFG_OR2_PRELIM 0xfff00d24
396#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
397#define CFG_OR3_PRELIM 0xffff8f44
398#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
399#define CFG_OR4_PRELIM 0xffff0300
400#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
401#define CFG_OR5_PRELIM 0xffff8db0
402
403/*
404 * Memory Periodic Timer Prescaler
405 *
406 * The Divider for PTA (refresh timer) configuration is based on an
407 * example SDRAM configuration (64 MBit, one bank). The adjustment to
408 * the number of chip selects (NCS) and the actually needed refresh
409 * rate is done by setting MPTPR.
410 *
411 * PTA is calculated from
412 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
413 *
414 * gclk CPU clock (not bus clock!)
415 * Trefresh Refresh cycle * 4 (four word bursts used)
416 *
417 * 4096 Rows from SDRAM example configuration
418 * 1000 factor s -> ms
419 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
420 * 4 Number of refresh cycles per period
421 * 64 Refresh cycle in ms per number of rows
422 * --------------------------------------------
423 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
424 *
425 * 50 MHz => 50.000.000 / Divider = 98
426 * 66 Mhz => 66.000.000 / Divider = 129
427 * 80 Mhz => 80.000.000 / Divider = 156
428 * 100 Mhz => 100.000.000 / Divider = 195
429 */
430
431#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
432#define CFG_MAMR_PTA 98
433
434/*
435 * For 16 MBit, refresh rates could be 31.3 us
436 * (= 64 ms / 2K = 125 / quad bursts).
437 * For a simpler initialization, 15.6 us is used instead.
438 *
439 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
440 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
441 */
442#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
443#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
444
445/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
446#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
447#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
448
449/*
450 * MAMR settings for SDRAM
451 */
452
453/* 8 column SDRAM */
454#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
455 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
457/* 9 column SDRAM */
458#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
459 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
461
462#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */
463#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */
464
465/*-----------------------------------------------------------------------
466 * I2C stuff
467 */
468
469/* enable I2C and select the hardware/software driver */
470#undef CONFIG_HARD_I2C /* I2C with hardware support */
471#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
472
473#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
474#define CFG_I2C_SLAVE 0xFE
475
476#ifdef CONFIG_SOFT_I2C
477/*
478 * Software (bit-bang) I2C driver configuration
479 */
480#define PB_SCL 0x00000020 /* PB 26 */
481#define PB_SDA 0x00000010 /* PB 27 */
482
483#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
484#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
485#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
486#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
487#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
488 else immr->im_cpm.cp_pbdat &= ~PB_SDA
489#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
490 else immr->im_cpm.cp_pbdat &= ~PB_SCL
491#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
492#endif /* CONFIG_SOFT_I2C */
493
494/*-----------------------------------------------------------------------
495 * I2C EEPROM (24C164)
496 */
497#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
498#define CFG_I2C_EEPROM_ADDR_LEN 1
499#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
500#define CFG_EEPROM_PAGE_WRITE_BITS 4
501
502/*
503 * Internal Definitions
504 *
505 * Boot Flags
506 */
507#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
508#define BOOTFLAG_WARM 0x02 /* Software reboot */
509
510#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
511#define FEC_ENET
512#define CONFIG_MII
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500513#define CONFIG_MII_INIT 1
wdenkf7d15722004-12-18 22:35:43 +0000514#define CFG_DISCOVER_PHY 1
515
516#endif /* __CONFIG_H */