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Michal Simek78d19a32009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek89c53892008-03-28 12:41:56 +01004 *
Michal Simek89c53892008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Michal Simek78d19a32009-09-07 09:08:02 +02008 */
Michal Simek89c53892008-03-28 12:41:56 +01009
10#include <common.h>
11#include <net.h>
12#include <config.h>
Michal Simek042272a2010-10-11 11:41:47 +100013#include <malloc.h>
Michal Simek89c53892008-03-28 12:41:56 +010014#include <asm/io.h>
Michal Simek7fd70822012-06-28 21:37:57 +000015#include <fdtdec.h>
16
Michal Simek89c53892008-03-28 12:41:56 +010017#undef DEBUG
18
Michal Simek89c53892008-03-28 12:41:56 +010019#define ENET_ADDR_LENGTH 6
20
21/* EmacLite constants */
22#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
23#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
24#define XEL_TSR_OFFSET 0x07FC /* Tx status */
25#define XEL_RSR_OFFSET 0x17FC /* Rx status */
26#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
27
28/* Xmit complete */
29#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30/* Xmit interrupt enable bit */
31#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
32/* Buffer is active, SW bit only */
33#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
34/* Program the MAC address */
35#define XEL_TSR_PROGRAM_MASK 0x00000002UL
36/* define for programming the MAC address into the EMAC Lite */
37#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
38
39/* Transmit packet length upper byte */
40#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
41/* Transmit packet length lower byte */
42#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
43
44/* Recv complete */
45#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
46/* Recv interrupt enable bit */
47#define XEL_RSR_RECV_IE_MASK 0x00000008UL
48
Michal Simek773cfa82011-08-25 12:47:56 +020049struct xemaclite {
Michal Simek042272a2010-10-11 11:41:47 +100050 u32 nexttxbuffertouse; /* Next TX buffer to write to */
51 u32 nextrxbuffertouse; /* Next RX buffer to read from */
Michal Simek947324b2011-09-12 21:10:01 +000052 u32 txpp; /* TX ping pong buffer */
53 u32 rxpp; /* RX ping pong buffer */
Michal Simek773cfa82011-08-25 12:47:56 +020054};
Michal Simek89c53892008-03-28 12:41:56 +010055
Clive Stubbingsf2a7806f2008-10-27 15:05:00 +000056static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
Michal Simek89c53892008-03-28 12:41:56 +010057
Michal Simek5ac83802011-09-12 21:10:05 +000058static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010059{
Michal Simek042272a2010-10-11 11:41:47 +100060 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +010061 u32 alignbuffer;
62 u32 *to32ptr;
63 u32 *from32ptr;
64 u8 *to8ptr;
65 u8 *from8ptr;
66
67 from32ptr = (u32 *) srcptr;
68
69 /* Word aligned buffer, no correction needed. */
70 to32ptr = (u32 *) destptr;
71 while (bytecount > 3) {
72 *to32ptr++ = *from32ptr++;
73 bytecount -= 4;
74 }
75 to8ptr = (u8 *) to32ptr;
76
77 alignbuffer = *from32ptr++;
Michal Simek5ac83802011-09-12 21:10:05 +000078 from8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +010079
Michal Simek5ac83802011-09-12 21:10:05 +000080 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +010081 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +010082}
83
Michal Simek5ac83802011-09-12 21:10:05 +000084static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010085{
Michal Simek042272a2010-10-11 11:41:47 +100086 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +010087 u32 alignbuffer;
88 u32 *to32ptr = (u32 *) destptr;
89 u32 *from32ptr;
90 u8 *to8ptr;
91 u8 *from8ptr;
92
93 from32ptr = (u32 *) srcptr;
94 while (bytecount > 3) {
95
96 *to32ptr++ = *from32ptr++;
97 bytecount -= 4;
98 }
99
100 alignbuffer = 0;
Michal Simek5ac83802011-09-12 21:10:05 +0000101 to8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100102 from8ptr = (u8 *) from32ptr;
103
Michal Simek5ac83802011-09-12 21:10:05 +0000104 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100105 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100106
107 *to32ptr++ = alignbuffer;
108}
109
Michal Simek042272a2010-10-11 11:41:47 +1000110static void emaclite_halt(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100111{
Michal Simek5ac83802011-09-12 21:10:05 +0000112 debug("eth_halt\n");
Michal Simek89c53892008-03-28 12:41:56 +0100113}
114
Michal Simek042272a2010-10-11 11:41:47 +1000115static int emaclite_init(struct eth_device *dev, bd_t *bis)
Michal Simek89c53892008-03-28 12:41:56 +0100116{
Michal Simek947324b2011-09-12 21:10:01 +0000117 struct xemaclite *emaclite = dev->priv;
Michal Simek5ac83802011-09-12 21:10:05 +0000118 debug("EmacLite Initialization Started\n");
Michal Simek89c53892008-03-28 12:41:56 +0100119
120/*
121 * TX - TX_PING & TX_PONG initialization
122 */
123 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200124 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek89c53892008-03-28 12:41:56 +0100125 /* Copy MAC address */
Michal Simek5ac83802011-09-12 21:10:05 +0000126 xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100127 /* Set the length */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200128 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100129 /* Update the MAC address in the EMAC Lite */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200130 out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
Michal Simek89c53892008-03-28 12:41:56 +0100131 /* Wait for EMAC Lite to finish with the MAC address update */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200132 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
133 XEL_TSR_PROG_MAC_ADDR) != 0)
134 ;
Michal Simek89c53892008-03-28 12:41:56 +0100135
Michal Simek947324b2011-09-12 21:10:01 +0000136 if (emaclite->txpp) {
137 /* The same operation with PONG TX */
138 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
139 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
140 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
141 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
142 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
143 XEL_TSR_PROG_MAC_ADDR);
144 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
145 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
146 ;
147 }
Michal Simek89c53892008-03-28 12:41:56 +0100148
149/*
150 * RX - RX_PING & RX_PONG initialization
151 */
152 /* Write out the value to flush the RX buffer */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200153 out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
Michal Simek947324b2011-09-12 21:10:01 +0000154
155 if (emaclite->rxpp)
156 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
157 XEL_RSR_RECV_IE_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100158
Michal Simek5ac83802011-09-12 21:10:05 +0000159 debug("EmacLite Initialization complete\n");
Michal Simek89c53892008-03-28 12:41:56 +0100160 return 0;
161}
162
Michal Simek773cfa82011-08-25 12:47:56 +0200163static int xemaclite_txbufferavailable(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100164{
165 u32 reg;
166 u32 txpingbusy;
167 u32 txpongbusy;
Michal Simek773cfa82011-08-25 12:47:56 +0200168 struct xemaclite *emaclite = dev->priv;
169
Michal Simek89c53892008-03-28 12:41:56 +0100170 /*
171 * Read the other buffer register
172 * and determine if the other buffer is available
173 */
Michal Simek773cfa82011-08-25 12:47:56 +0200174 reg = in_be32 (dev->iobase +
175 emaclite->nexttxbuffertouse + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100176 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
177 XEL_TSR_XMIT_BUSY_MASK);
178
Michal Simek773cfa82011-08-25 12:47:56 +0200179 reg = in_be32 (dev->iobase +
180 (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100181 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
182 XEL_TSR_XMIT_BUSY_MASK);
183
Michal Simek5ac83802011-09-12 21:10:05 +0000184 return !(txpingbusy && txpongbusy);
Michal Simek89c53892008-03-28 12:41:56 +0100185}
186
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000187static int emaclite_send(struct eth_device *dev, void *ptr, int len)
Michal Simek042272a2010-10-11 11:41:47 +1000188{
189 u32 reg;
190 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200191 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100192
Michal Simek042272a2010-10-11 11:41:47 +1000193 u32 maxtry = 1000;
Michal Simek89c53892008-03-28 12:41:56 +0100194
Michal Simek80439252011-09-12 21:10:04 +0000195 if (len > PKTSIZE)
196 len = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100197
Michal Simek773cfa82011-08-25 12:47:56 +0200198 while (!xemaclite_txbufferavailable(dev) && maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000199 udelay(10);
Michal Simek89c53892008-03-28 12:41:56 +0100200 maxtry--;
201 }
202
203 if (!maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000204 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100205 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200206 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek947324b2011-09-12 21:10:01 +0000207 if (emaclite->txpp) {
208 out_be32 (dev->iobase + XEL_TSR_OFFSET +
209 XEL_BUFFER_OFFSET, 0);
210 }
Michal Simek95efa792011-03-08 04:25:53 +0000211 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100212 }
213
214 /* Determine the expected TX buffer address */
Michal Simek773cfa82011-08-25 12:47:56 +0200215 baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
Michal Simek89c53892008-03-28 12:41:56 +0100216
217 /* Determine if the expected buffer address is empty */
218 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
219 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
220 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
221 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
222
Michal Simek947324b2011-09-12 21:10:01 +0000223 if (emaclite->txpp)
224 emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
225
Michal Simek5ac83802011-09-12 21:10:05 +0000226 debug("Send packet from 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100227 /* Write the frame to the buffer */
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000228 xemaclite_alignedwrite(ptr, baseaddress, len);
Michal Simek89c53892008-03-28 12:41:56 +0100229 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
230 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
231 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
232 reg |= XEL_TSR_XMIT_BUSY_MASK;
Michal Simek5ac83802011-09-12 21:10:05 +0000233 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
Michal Simek89c53892008-03-28 12:41:56 +0100234 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
Michal Simek89c53892008-03-28 12:41:56 +0100235 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
Michal Simek95efa792011-03-08 04:25:53 +0000236 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100237 }
Michal Simek947324b2011-09-12 21:10:01 +0000238
239 if (emaclite->txpp) {
240 /* Switch to second buffer */
241 baseaddress ^= XEL_BUFFER_OFFSET;
242 /* Determine if the expected buffer address is empty */
Michal Simek89c53892008-03-28 12:41:56 +0100243 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
Michal Simek947324b2011-09-12 21:10:01 +0000244 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
245 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
246 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
247 debug("Send packet from 0x%x\n", baseaddress);
248 /* Write the frame to the buffer */
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000249 xemaclite_alignedwrite(ptr, baseaddress, len);
Michal Simek947324b2011-09-12 21:10:01 +0000250 out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
251 (XEL_TPLR_LENGTH_MASK_HI |
252 XEL_TPLR_LENGTH_MASK_LO)));
253 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
254 reg |= XEL_TSR_XMIT_BUSY_MASK;
255 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
256 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
257 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
258 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100259 }
Michal Simek89c53892008-03-28 12:41:56 +0100260 }
Michal Simek947324b2011-09-12 21:10:01 +0000261
Michal Simek5ac83802011-09-12 21:10:05 +0000262 puts("Error while sending frame\n");
Michal Simek95efa792011-03-08 04:25:53 +0000263 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100264}
265
Michal Simek042272a2010-10-11 11:41:47 +1000266static int emaclite_recv(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100267{
Michal Simek042272a2010-10-11 11:41:47 +1000268 u32 length;
269 u32 reg;
270 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200271 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100272
Michal Simek773cfa82011-08-25 12:47:56 +0200273 baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
Michal Simek89c53892008-03-28 12:41:56 +0100274 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
Michal Simek5ac83802011-09-12 21:10:05 +0000275 debug("Testing data at address 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100276 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
Michal Simek947324b2011-09-12 21:10:01 +0000277 if (emaclite->rxpp)
278 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
Michal Simek89c53892008-03-28 12:41:56 +0100279 } else {
Michal Simek947324b2011-09-12 21:10:01 +0000280
281 if (!emaclite->rxpp) {
Michal Simek5ac83802011-09-12 21:10:05 +0000282 debug("No data was available - address 0x%x\n",
Michal Simek947324b2011-09-12 21:10:01 +0000283 baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100284 return 0;
Michal Simek947324b2011-09-12 21:10:01 +0000285 } else {
286 baseaddress ^= XEL_BUFFER_OFFSET;
287 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
288 if ((reg & XEL_RSR_RECV_DONE_MASK) !=
289 XEL_RSR_RECV_DONE_MASK) {
290 debug("No data was available - address 0x%x\n",
291 baseaddress);
292 return 0;
293 }
Michal Simek89c53892008-03-28 12:41:56 +0100294 }
Michal Simek89c53892008-03-28 12:41:56 +0100295 }
296 /* Get the length of the frame that arrived */
Michal Simek3f91ec02010-10-11 11:41:46 +1000297 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
Michal Simek89c53892008-03-28 12:41:56 +0100298 0xFFFF0000 ) >> 16) {
299 case 0x806:
300 length = 42 + 20; /* FIXME size of ARP */
Michal Simek5ac83802011-09-12 21:10:05 +0000301 debug("ARP Packet\n");
Michal Simek89c53892008-03-28 12:41:56 +0100302 break;
303 case 0x800:
304 length = 14 + 14 +
Michal Simek5ac83802011-09-12 21:10:05 +0000305 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
306 0x10))) & 0xFFFF0000) >> 16);
307 /* FIXME size of IP packet */
Michal Simek89c53892008-03-28 12:41:56 +0100308 debug ("IP Packet\n");
309 break;
310 default:
Michal Simek80439252011-09-12 21:10:04 +0000311 debug("Other Packet\n");
312 length = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100313 break;
314 }
315
Michal Simek5ac83802011-09-12 21:10:05 +0000316 xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
Michal Simek89c53892008-03-28 12:41:56 +0100317 etherrxbuff, length);
318
319 /* Acknowledge the frame */
320 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
321 reg &= ~XEL_RSR_RECV_DONE_MASK;
322 out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
323
Michal Simek5ac83802011-09-12 21:10:05 +0000324 debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500325 net_process_received_packet((uchar *)etherrxbuff, length);
Michal Simek95efa792011-03-08 04:25:53 +0000326 return length;
Michal Simek89c53892008-03-28 12:41:56 +0100327
328}
Michal Simek042272a2010-10-11 11:41:47 +1000329
Michal Simekc1044a12011-10-12 23:23:22 +0000330int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
331 int txpp, int rxpp)
Michal Simek042272a2010-10-11 11:41:47 +1000332{
333 struct eth_device *dev;
Michal Simek773cfa82011-08-25 12:47:56 +0200334 struct xemaclite *emaclite;
Michal Simek042272a2010-10-11 11:41:47 +1000335
Michal Simek28ae02e2011-08-25 12:28:47 +0200336 dev = calloc(1, sizeof(*dev));
Michal Simek042272a2010-10-11 11:41:47 +1000337 if (dev == NULL)
Michal Simek95efa792011-03-08 04:25:53 +0000338 return -1;
Michal Simek042272a2010-10-11 11:41:47 +1000339
Michal Simek773cfa82011-08-25 12:47:56 +0200340 emaclite = calloc(1, sizeof(struct xemaclite));
341 if (emaclite == NULL) {
342 free(dev);
343 return -1;
344 }
345
346 dev->priv = emaclite;
347
Michal Simekc1044a12011-10-12 23:23:22 +0000348 emaclite->txpp = txpp;
349 emaclite->rxpp = rxpp;
Michal Simek947324b2011-09-12 21:10:01 +0000350
Michal Simek9b947552011-10-12 23:23:21 +0000351 sprintf(dev->name, "Xelite.%lx", base_addr);
Michal Simek042272a2010-10-11 11:41:47 +1000352
353 dev->iobase = base_addr;
Michal Simek042272a2010-10-11 11:41:47 +1000354 dev->init = emaclite_init;
355 dev->halt = emaclite_halt;
356 dev->send = emaclite_send;
357 dev->recv = emaclite_recv;
358
359 eth_register(dev);
360
Michal Simek95efa792011-03-08 04:25:53 +0000361 return 1;
Michal Simek042272a2010-10-11 11:41:47 +1000362}
Michal Simek7fd70822012-06-28 21:37:57 +0000363
364#ifdef CONFIG_OF_CONTROL
Michal Simek0c9c99a2014-02-24 11:16:28 +0100365int xilinx_emaclite_of_init(const void *blob)
Michal Simek7fd70822012-06-28 21:37:57 +0000366{
367 int offset = 0;
368 u32 ret = 0;
369 u32 reg;
370
371 do {
Michal Simek0c9c99a2014-02-24 11:16:28 +0100372 offset = fdt_node_offset_by_compatible(blob, offset,
Michal Simek7fd70822012-06-28 21:37:57 +0000373 "xlnx,xps-ethernetlite-1.00.a");
374 if (offset != -1) {
Michal Simek0c9c99a2014-02-24 11:16:28 +0100375 reg = fdtdec_get_addr(blob, offset, "reg");
Michal Simek7fd70822012-06-28 21:37:57 +0000376 if (reg != FDT_ADDR_T_NONE) {
Michal Simek0c9c99a2014-02-24 11:16:28 +0100377 u32 rxpp = fdtdec_get_int(blob, offset,
Michal Simek7fd70822012-06-28 21:37:57 +0000378 "xlnx,rx-ping-pong", 0);
Michal Simek0c9c99a2014-02-24 11:16:28 +0100379 u32 txpp = fdtdec_get_int(blob, offset,
Michal Simek7fd70822012-06-28 21:37:57 +0000380 "xlnx,tx-ping-pong", 0);
Michal Simek0c9c99a2014-02-24 11:16:28 +0100381 ret |= xilinx_emaclite_initialize(NULL, reg,
Michal Simek7fd70822012-06-28 21:37:57 +0000382 txpp, rxpp);
Michal Simek0c9c99a2014-02-24 11:16:28 +0100383 } else {
384 debug("EMACLITE: Can't get base address\n");
385 return -1;
Michal Simek7fd70822012-06-28 21:37:57 +0000386 }
387 }
388 } while (offset != -1);
389
390 return ret;
391}
392#endif