blob: 2a01ea061fbb0e92b48915bde6b7f2e5c07cebdc [file] [log] [blame]
Lars Povlsenfd6e0b02019-01-08 10:38:33 +01001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs spi driver
4 *
5 * Copyright (c) 2018 Microsemi Corporation
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Lars Povlsenfd6e0b02019-01-08 10:38:33 +010012#include <malloc.h>
13#include <spi.h>
Lars Povlsenfd6e0b02019-01-08 10:38:33 +010014#include <asm/gpio.h>
15#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Lars Povlsenfd6e0b02019-01-08 10:38:33 +010017#include <linux/delay.h>
18
19struct mscc_bb_priv {
20 void __iomem *regs;
21 u32 deactivate_delay_us;
22 bool cs_active; /* State flag as to whether CS is asserted */
23 int cs_num;
24 u32 svalue; /* Value to start transfer with */
25 u32 clk1; /* Clock value start */
26 u32 clk2; /* Clock value 2nd phase */
27};
28
29/* Delay 24 instructions for this particular application */
30#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
31
32static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
33{
34 if (!priv->cs_active) {
35 int cpha = mode & SPI_CPHA;
36 u32 cs_value;
37
38 priv->cs_num = cs;
39
40 if (cpha) {
41 /* Initial clock starts SCK=1 */
42 priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
43 priv->clk2 = 0;
44 } else {
45 /* Initial clock starts SCK=0 */
46 priv->clk1 = 0;
47 priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
48 }
49
50 /* Enable bitbang, SCK_OE, SDO_OE */
51 priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
52 ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
53 ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
54
55 /* Add CS */
56 if (cs >= 0) {
57 cs_value =
58 ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
59 ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
60 } else {
61 cs_value = 0;
62 }
63
64 priv->svalue |= cs_value;
65
66 /* Enable the CS in HW, Initial clock value */
67 writel(priv->svalue | priv->clk2, priv->regs);
68
69 priv->cs_active = true;
70 debug("Activated CS%d\n", priv->cs_num);
71 }
72
73 return 0;
74}
75
76static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
77{
78 if (priv->cs_active) {
79 /* Keep driving the CLK to its current value while
80 * actively deselecting CS.
81 */
82 u32 value = readl(priv->regs);
83
84 value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
85 writel(value, priv->regs);
86 hold_time_delay();
87
88 /* Stop driving the clock, but keep CS with nCS == 1 */
89 value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
90 writel(value, priv->regs);
91
92 /* Deselect hold time delay */
93 if (deact_delay)
94 udelay(deact_delay);
95
96 /* Drop everything */
97 writel(0, priv->regs);
98
99 priv->cs_active = false;
100 debug("Deactivated CS%d\n", priv->cs_num);
101 }
102
103 return 0;
104}
105
106int mscc_bb_spi_claim_bus(struct udevice *dev)
107{
108 return 0;
109}
110
111int mscc_bb_spi_release_bus(struct udevice *dev)
112{
113 return 0;
114}
115
116int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
117 const void *dout, void *din, unsigned long flags)
118{
119 struct udevice *bus = dev_get_parent(dev);
Simon Glass8a8d24b2020-12-03 16:55:23 -0700120 struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
Lars Povlsenfd6e0b02019-01-08 10:38:33 +0100121 struct mscc_bb_priv *priv = dev_get_priv(bus);
122 u32 i, count;
123 const u8 *txd = dout;
124 u8 *rxd = din;
125
126 debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
127 dev->parent->name, dev->name, plat->cs, plat->mode, dout,
128 din, bitlen);
129
130 if (flags & SPI_XFER_BEGIN)
131 mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
132
133 count = bitlen / 8;
134 for (i = 0; i < count; i++) {
135 u32 rx = 0, mask = 0x80, value;
136
137 while (mask) {
138 /* Initial condition: CLK is low. */
139 value = priv->svalue;
140 if (txd && txd[i] & mask)
141 value |= ICPU_SW_MODE_SW_SPI_SDO;
142
143 /* Drive data while taking CLK low. The device
144 * we're accessing will sample on the
145 * following rising edge and will output data
146 * on this edge for us to be sampled at the
147 * end of this loop.
148 */
149 writel(value | priv->clk1, priv->regs);
150
151 /* Wait for t_setup. All devices do have a
152 * setup-time, so we always insert some delay
153 * here. Some devices have a very long
154 * setup-time, which can be adjusted by the
155 * user through vcoreiii_device->delay.
156 */
157 hold_time_delay();
158
159 /* Drive the clock high. */
160 writel(value | priv->clk2, priv->regs);
161
162 /* Wait for t_hold. See comment about t_setup
163 * above.
164 */
165 hold_time_delay();
166
167 /* We sample as close to the next falling edge
168 * as possible.
169 */
170 value = readl(priv->regs);
171 if (value & ICPU_SW_MODE_SW_SPI_SDI)
172 rx |= mask;
173 mask >>= 1;
174 }
175 if (rxd) {
176 debug("Read 0x%02x\n", rx);
177 rxd[i] = (u8)rx;
178 }
179 debug("spi_xfer: byte %d/%d\n", i + 1, count);
180 }
181
182 debug("spi_xfer: done\n");
183
184 if (flags & SPI_XFER_END)
185 mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
186
187 return 0;
188}
189
190int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
191{
192 /* Accept any speed */
193 return 0;
194}
195
196int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
197{
198 return 0;
199}
200
201static const struct dm_spi_ops mscc_bb_ops = {
202 .claim_bus = mscc_bb_spi_claim_bus,
203 .release_bus = mscc_bb_spi_release_bus,
204 .xfer = mscc_bb_spi_xfer,
205 .set_speed = mscc_bb_spi_set_speed,
206 .set_mode = mscc_bb_spi_set_mode,
207};
208
209static const struct udevice_id mscc_bb_ids[] = {
210 { .compatible = "mscc,luton-bb-spi" },
211 { }
212};
213
214static int mscc_bb_spi_probe(struct udevice *bus)
215{
216 struct mscc_bb_priv *priv = dev_get_priv(bus);
217
218 debug("%s: loaded, priv %p\n", __func__, priv);
219
220 priv->regs = (void __iomem *)dev_read_addr(bus);
221
222 priv->deactivate_delay_us =
223 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
224
225 priv->cs_active = false;
226
227 return 0;
228}
229
230U_BOOT_DRIVER(mscc_bb) = {
231 .name = "mscc_bb",
232 .id = UCLASS_SPI,
233 .of_match = mscc_bb_ids,
234 .ops = &mscc_bb_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700235 .priv_auto = sizeof(struct mscc_bb_priv),
Lars Povlsenfd6e0b02019-01-08 10:38:33 +0100236 .probe = mscc_bb_spi_probe,
237};