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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 79679d80021ab095e639e250ca472fe526da02e2 / . / cpu / mpc85xx / release.S
blob: 3b7366ff692c1dbbddd36ac1e3b4382a114bb0f6 [file] [log] [blame]
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]1#include <config.h>
2#include <mpc85xx.h>
3#include <version.h>
4
5#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
6
7#include <ppc_asm.tmpl>
8#include <ppc_defs.h>
9
10#include <asm/cache.h>
11#include <asm/mmu.h>
12
13/* To boot secondary cpus, we need a place for them to start up.
14 * Normally, they start at 0xfffffffc, but that's usually the
15 * firmware, and we don't want to have to run the firmware again.
16 * Instead, the primary cpu will set the BPTR to point here to
17 * this page. We then set up the core, and head to
18 * start_secondary. Note that this means that the code below
19 * must never exceed 1023 instructions (the branch at the end
20 * would then be the 1024th).
21 */
22 .globl __secondary_start_page
23 .align 12
24__secondary_start_page:
25/* First do some preliminary setup */
26 lis r3, HID0_EMCP@h /* enable machine check */
27 ori r3,r3,HID0_TBEN@l /* enable Timebase */
28#ifdef CONFIG_PHYS_64BIT
29 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
30#endif
31 mtspr SPRN_HID0,r3
32
33 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
34 mtspr SPRN_HID1,r3
35
36 /* Enable branch prediction */
37 li r3,0x201
38 mtspr SPRN_BUCSR,r3
39
40 /* Enable/invalidate the I-Cache */
41 mfspr r0,SPRN_L1CSR1
42 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
43 mtspr SPRN_L1CSR1,r0
44 isync
45
46 /* Enable/invalidate the D-Cache */
47 mfspr r0,SPRN_L1CSR0
48 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
49 msync
50 isync
51 mtspr SPRN_L1CSR0,r0
52 isync
53
54#define toreset(x) (x - __secondary_start_page + 0xfffff000)
55
56 /* get our PIR to figure out our table entry */
57 lis r3,toreset(__spin_table)@h
58 ori r3,r3,toreset(__spin_table)@l
59
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]60 /* r10 has the base address for the entry */
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]61 mfspr r0,SPRN_PIR
62 mr r4,r0
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]63 slwi r8,r4,5
64 add r10,r3,r8
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]65
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]66#define EPAPR_MAGIC (0x45504150)
67#define ENTRY_ADDR_UPPER 0
68#define ENTRY_ADDR_LOWER 4
69#define ENTRY_R3_UPPER 8
70#define ENTRY_R3_LOWER 12
71#define ENTRY_RESV 16
72#define ENTRY_PIR 20
73#define ENTRY_R6_UPPER 24
74#define ENTRY_R6_LOWER 28
75#define ENTRY_SIZE 32
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]76
77 /* setup the entry */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]78 li r3,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]79 li r8,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]80 stw r0,ENTRY_PIR(r10)
81 stw r3,ENTRY_ADDR_UPPER(r10)
82 stw r8,ENTRY_ADDR_LOWER(r10)
83 stw r3,ENTRY_R3_UPPER(r10)
84 stw r4,ENTRY_R3_LOWER(r10)
85 stw r3,ENTRY_R6_UPPER(r10)
86 stw r3,ENTRY_R6_LOWER(r10)
87
88 /* setup mapping for AS = 1, and jump there */
89 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
90 mtspr SPRN_MAS0,r11
91 lis r11,(MAS1_VALID|MAS1_IPROT)@h
92 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
93 mtspr SPRN_MAS1,r11
94 lis r11,(0xfffff000|MAS2_I)@h
95 ori r11,r11,(0xfffff000|MAS2_I)@l
96 mtspr SPRN_MAS2,r11
97 lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
98 ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
99 mtspr SPRN_MAS3,r11
100 tlbwe
101
102 bl 1f
1031: mflr r11
104 addi r11,r11,28
105 mfmsr r13
106 ori r12,r13,MSR_IS|MSR_DS@l
107
108 mtspr SPRN_SRR0,r11
109 mtspr SPRN_SRR1,r12
110 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]111
112 /* spin waiting for addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]1132:
114 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]115 andi. r11,r4,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]116 bne 2b
117
118 /* get the upper bits of the addr */
119 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]120
121 /* setup branch addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]122 mtspr SPRN_SRR0,r4
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]123
124 /* mark the entry as released */
125 li r8,3
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]126 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]127
128 /* mask by ~64M to setup our tlb we will jump to */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]129 rlwinm r12,r4,0,0,5
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]130
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]131 /* setup r3, r4, r5, r6, r7, r8, r9 */
132 lwz r3,ENTRY_R3_LOWER(r10)
133 li r4,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]134 li r5,0
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]135 lwz r6,ENTRY_R6_LOWER(r10)
136 lis r7,(64*1024*1024)@h
137 li r8,0
138 li r9,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]139
140 /* load up the pir */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]141 lwz r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]142 mtspr SPRN_PIR,r0
143 mfspr r0,SPRN_PIR
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]144 stw r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]145
146/*
147 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
148 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
149 * second mapping that maps addr 1:1 for 64M, and then we jump to
150 * addr
151 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]152 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
153 mtspr SPRN_MAS0,r10
154 lis r10,(MAS1_VALID|MAS1_IPROT)@h
155 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
156 mtspr SPRN_MAS1,r10
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]157 /* WIMGE = 0b00000 for now */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]158 mtspr SPRN_MAS2,r12
159 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
160 mtspr SPRN_MAS3,r12
161#ifdef CONFIG_ENABLE_36BIT_PHYS
162 mtspr SPRN_MAS7,r11
163#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]164 tlbwe
165
166/* Now we have another mapping for this page, so we jump to that
167 * mapping
168 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]169 mtspr SPRN_SRR1,r13
170 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]171
172 .align 3
173 .globl __spin_table
174__spin_table:
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame^]175 .space CONFIG_NR_CPUS*ENTRY_SIZE
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]176
177 /* Fill in the empty space. The actual reset vector is
178 * the last word of the page */
179__secondary_start_code_end:
180 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
181__secondary_reset_vector:
182 b __secondary_start_page