blob: fdce2c2c10ec85c4a291532f927eae4a0b5627c9 [file] [log] [blame]
Michal Simek293eb332013-04-22 14:56:49 +02001/*
2 * (C) Copyright 2013 Inc.
3 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek293eb332013-04-22 14:56:49 +02007 */
8
9#include <common.h>
Michal Simek345d3c02014-02-24 11:16:31 +010010#include <fdtdec.h>
11#include <libfdt.h>
Michal Simek293eb332013-04-22 14:56:49 +020012#include <malloc.h>
13#include <sdhci.h>
14#include <asm/arch/sys_proto.h>
15
16int zynq_sdhci_init(u32 regbase)
17{
18 struct sdhci_host *host = NULL;
19
20 host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
21 if (!host) {
22 printf("zynq_sdhci_init: sdhci_host malloc fail\n");
23 return 1;
24 }
25
26 host->name = "zynq_sdhci";
27 host->ioaddr = (void *)regbase;
Siva Durga Prasad Paladuguf9ec45d2014-01-22 09:17:09 +010028 host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD |
29 SDHCI_QUIRK_BROKEN_R1B;
Michal Simek293eb332013-04-22 14:56:49 +020030 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
31
32 host->host_caps = MMC_MODE_HC;
33
34 add_sdhci(host, 52000000, 52000000 >> 9);
35 return 0;
36}
Michal Simek345d3c02014-02-24 11:16:31 +010037
38#ifdef CONFIG_OF_CONTROL
39int zynq_sdhci_of_init(const void *blob)
40{
41 int offset = 0;
42 u32 ret = 0;
43 u32 reg;
44
45 debug("ZYNQ SDHCI: Initialization\n");
46
47 do {
48 offset = fdt_node_offset_by_compatible(blob, offset,
49 "arasan,sdhci-8.9a");
50 if (offset != -1) {
51 reg = fdtdec_get_addr(blob, offset, "reg");
52 if (reg != FDT_ADDR_T_NONE) {
53 ret |= zynq_sdhci_init(reg);
54 } else {
55 debug("ZYNQ SDHCI: Can't get base address\n");
56 return -1;
57 }
58 }
59 } while (offset != -1);
60
61 return ret;
62}
63#endif