blob: fbf97632c6df4707a05ab137454a2aa69d2c50f1 [file] [log] [blame]
Ajay Bhargav79788bb2011-09-13 22:21:58 +05301/*
2 * (C) Copyright 2011
3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
5 *
6 * (C) Copyright 2010
7 * Marvell Semiconductor <www.marvell.com>
8 * Contributor: Mahavir Jain <mjain@marvell.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 * MA 02110-1301 USA
27 */
28
29#include <common.h>
30#include <net.h>
31#include <malloc.h>
32#include <miiphy.h>
33#include <netdev.h>
34#include <asm/types.h>
35#include <asm/byteorder.h>
36#include <linux/err.h>
37#include <linux/mii.h>
38#include <asm/io.h>
39#include <asm/arch/armada100.h>
40#include "armada100_fec.h"
41
42#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
43
44#ifdef DEBUG
45static int eth_dump_regs(struct eth_device *dev)
46{
47 struct armdfec_device *darmdfec = to_darmdfec(dev);
48 struct armdfec_reg *regs = darmdfec->regs;
49 unsigned int i = 0;
50
51 printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
52 printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
53 for (i = 0x400; i <= 0x4e4; i += 4)
54 printf("offset: 0x%x, value: 0x%x\n",
55 i, readl(ARMD1_FEC_BASE + i));
56 return 0;
57}
58#endif
59
60static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
61{
62 u32 timeout = PHY_WAIT_ITERATIONS;
63 u32 reg_val;
64
65 while (--timeout) {
66 reg_val = readl(reg);
67 if (cond && (reg_val & flag))
68 break;
69 else if (!cond && !(reg_val & flag))
70 break;
71 udelay(PHY_WAIT_MICRO_SECONDS);
72 }
73 return !timeout;
74}
75
76static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
77 u16 *value)
78{
79 struct eth_device *dev = eth_get_dev_by_name(devname);
80 struct armdfec_device *darmdfec = to_darmdfec(dev);
81 struct armdfec_reg *regs = darmdfec->regs;
82 u32 val;
83
84 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
85 val = readl(&regs->phyadr);
86 *value = val & 0x1f;
87 return 0;
88 }
89
90 /* check parameters */
91 if (phy_addr > PHY_MASK) {
92 printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
93 __func__, phy_addr);
94 return -EINVAL;
95 }
96 if (phy_reg > PHY_MASK) {
97 printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
98 __func__, phy_reg);
99 return -EINVAL;
100 }
101
102 /* wait for the SMI register to become available */
103 if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
104 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
105 return -1;
106 }
107
108 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);
109
110 /* now wait for the data to be valid */
111 if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, TRUE)) {
112 val = readl(&regs->smi);
113 printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
114 __func__, val);
115 return -1;
116 }
117 val = readl(&regs->smi);
118 *value = val & 0xffff;
119
120 return 0;
121}
122
123static int smi_reg_write(const char *devname,
124 u8 phy_addr, u8 phy_reg, u16 value)
125{
126 struct eth_device *dev = eth_get_dev_by_name(devname);
127 struct armdfec_device *darmdfec = to_darmdfec(dev);
128 struct armdfec_reg *regs = darmdfec->regs;
129
130 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
131 clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
132 return 0;
133 }
134
135 /* check parameters */
136 if (phy_addr > PHY_MASK) {
137 printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
138 return -EINVAL;
139 }
140 if (phy_reg > PHY_MASK) {
141 printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
142 return -EINVAL;
143 }
144
145 /* wait for the SMI register to become available */
146 if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
147 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
148 return -1;
149 }
150
151 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
152 &regs->smi);
153 return 0;
154}
155
156/*
157 * Abort any transmit and receive operations and put DMA
158 * in idle state. AT and AR bits are cleared upon entering
159 * in IDLE state. So poll those bits to verify operation.
160 */
161static void abortdma(struct eth_device *dev)
162{
163 struct armdfec_device *darmdfec = to_darmdfec(dev);
164 struct armdfec_reg *regs = darmdfec->regs;
165 int delay;
166 int maxretries = 40;
167 u32 tmp;
168
169 while (--maxretries) {
170 writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd);
171 udelay(100);
172
173 delay = 10;
174 while (--delay) {
175 tmp = readl(&regs->sdma_cmd);
176 if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
177 break;
178 udelay(10);
179 }
180 if (delay)
181 break;
182 }
183
184 if (!maxretries)
185 printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
186}
187
188static inline u32 nibble_swapping_32_bit(u32 x)
189{
190 return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
191}
192
193static inline u32 nibble_swapping_16_bit(u32 x)
194{
195 return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
196}
197
198static inline u32 flip_4_bits(u32 x)
199{
200 return ((x & 0x01) << 3) | ((x & 0x002) << 1)
201 | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
202}
203
204/*
205 * This function will calculate the hash function of the address.
206 * depends on the hash mode and hash size.
207 * Inputs
208 * mach - the 2 most significant bytes of the MAC address.
209 * macl - the 4 least significant bytes of the MAC address.
210 * Outputs
211 * return the calculated entry.
212 */
213static u32 hash_function(u32 mach, u32 macl)
214{
215 u32 hashresult;
216 u32 addrh;
217 u32 addrl;
218 u32 addr0;
219 u32 addr1;
220 u32 addr2;
221 u32 addr3;
222 u32 addrhswapped;
223 u32 addrlswapped;
224
225 addrh = nibble_swapping_16_bit(mach);
226 addrl = nibble_swapping_32_bit(macl);
227
228 addrhswapped = flip_4_bits(addrh & 0xf)
229 + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
230 + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
231 + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
232
233 addrlswapped = flip_4_bits(addrl & 0xf)
234 + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
235 + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
236 + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
237 + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
238 + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
239 + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
240 + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
241
242 addrh = addrhswapped;
243 addrl = addrlswapped;
244
245 addr0 = (addrl >> 2) & 0x03f;
246 addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
247 addr2 = (addrl >> 15) & 0x1ff;
248 addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
249
250 hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
251 hashresult = hashresult & 0x07ff;
252 return hashresult;
253}
254
255/*
256 * This function will add an entry to the address table.
257 * depends on the hash mode and hash size that was initialized.
258 * Inputs
259 * mach - the 2 most significant bytes of the MAC address.
260 * macl - the 4 least significant bytes of the MAC address.
261 * skip - if 1, skip this address.
262 * rd - the RD field in the address table.
263 * Outputs
264 * address table entry is added.
265 * 0 if success.
266 * -ENOSPC if table full
267 */
268static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
269 u32 macl, u32 rd, u32 skip, int del)
270{
271 struct addr_table_entry_t *entry, *start;
272 u32 newhi;
273 u32 newlo;
274 u32 i;
275
276 newlo = (((mach >> 4) & 0xf) << 15)
277 | (((mach >> 0) & 0xf) << 11)
278 | (((mach >> 12) & 0xf) << 7)
279 | (((mach >> 8) & 0xf) << 3)
280 | (((macl >> 20) & 0x1) << 31)
281 | (((macl >> 16) & 0xf) << 27)
282 | (((macl >> 28) & 0xf) << 23)
283 | (((macl >> 24) & 0xf) << 19)
284 | (skip << HTESKIP) | (rd << HTERDBIT)
285 | HTEVALID;
286
287 newhi = (((macl >> 4) & 0xf) << 15)
288 | (((macl >> 0) & 0xf) << 11)
289 | (((macl >> 12) & 0xf) << 7)
290 | (((macl >> 8) & 0xf) << 3)
291 | (((macl >> 21) & 0x7) << 0);
292
293 /*
294 * Pick the appropriate table, start scanning for free/reusable
295 * entries at the index obtained by hashing the specified MAC address
296 */
297 start = (struct addr_table_entry_t *)(darmdfec->htpr);
298 entry = start + hash_function(mach, macl);
299 for (i = 0; i < HOP_NUMBER; i++) {
300 if (!(entry->lo & HTEVALID)) {
301 break;
302 } else {
303 /* if same address put in same position */
304 if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
305 && (entry->hi == newhi))
306 break;
307 }
308 if (entry == start + 0x7ff)
309 entry = start;
310 else
311 entry++;
312 }
313
314 if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
315 (entry->hi != newhi) && del)
316 return 0;
317
318 if (i == HOP_NUMBER) {
319 if (!del) {
320 printf("ARMD100 FEC: (%s) table section is full\n",
321 __func__);
322 return -ENOSPC;
323 } else {
324 return 0;
325 }
326 }
327
328 /*
329 * Update the selected entry
330 */
331 if (del) {
332 entry->hi = 0;
333 entry->lo = 0;
334 } else {
335 entry->hi = newhi;
336 entry->lo = newlo;
337 }
338
339 return 0;
340}
341
342/*
343 * Create an addressTable entry from MAC address info
344 * found in the specifed net_device struct
345 *
346 * Input : pointer to ethernet interface network device structure
347 * Output : N/A
348 */
349static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
350 u8 *oaddr, u8 *addr)
351{
352 u32 mach;
353 u32 macl;
354
355 /* Delete old entry */
356 if (oaddr) {
357 mach = (oaddr[0] << 8) | oaddr[1];
358 macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
359 (oaddr[4] << 8) | oaddr[5];
360 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
361 }
362
363 /* Add new entry */
364 mach = (addr[0] << 8) | addr[1];
365 macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
366 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
367}
368
369/* Address Table Initialization */
370static void init_hashtable(struct eth_device *dev)
371{
372 struct armdfec_device *darmdfec = to_darmdfec(dev);
373 struct armdfec_reg *regs = darmdfec->regs;
374 memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
375 writel((u32)darmdfec->htpr, &regs->htpr);
376}
377
378/*
379 * This detects PHY chip from address 0-31 by reading PHY status
380 * registers. PHY chip can be connected at any of this address.
381 */
382static int ethernet_phy_detect(struct eth_device *dev)
383{
384 u32 val;
385 u16 tmp, mii_status;
386 u8 addr;
387
388 for (addr = 0; addr < 32; addr++) {
389 if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
390 /* try next phy */
391 continue;
392
393 /* invalid MII status. More validation required here... */
394 if (mii_status == 0 || mii_status == 0xffff)
395 /* try next phy */
396 continue;
397
398 if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
399 /* try next phy */
400 continue;
401
402 val = tmp << 16;
403 if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
404 /* try next phy */
405 continue;
406
407 val |= tmp;
408
409 if ((val & 0xfffffff0) != 0)
410 return addr;
411 }
412 return -1;
413}
414
415static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
416{
417 struct rx_desc *p_rx_desc;
418 int i;
419
420 /* initialize the Rx descriptors ring */
421 p_rx_desc = darmdfec->p_rxdesc;
422 for (i = 0; i < RINGSZ; i++) {
423 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
424 p_rx_desc->buf_size = PKTSIZE_ALIGN;
425 p_rx_desc->byte_cnt = 0;
426 p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
427 if (i == (RINGSZ - 1)) {
428 p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
429 } else {
430 p_rx_desc->nxtdesc_p = (struct rx_desc *)
431 ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
432 p_rx_desc = p_rx_desc->nxtdesc_p;
433 }
434 }
435 darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
436}
437
438static int armdfec_init(struct eth_device *dev, bd_t *bd)
439{
440 struct armdfec_device *darmdfec = to_darmdfec(dev);
441 struct armdfec_reg *regs = darmdfec->regs;
442 int phy_adr;
443
444 armdfec_init_rx_desc_ring(darmdfec);
445
446 /* Disable interrupts */
447 writel(0, &regs->im);
448 writel(0, &regs->ic);
449 /* Write to ICR to clear interrupts. */
450 writel(0, &regs->iwc);
451
452 /*
453 * Abort any transmit and receive operations and put DMA
454 * in idle state.
455 */
456 abortdma(dev);
457
458 /* Initialize address hash table */
459 init_hashtable(dev);
460
461 /* SDMA configuration */
462 writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
463 SDCR_RIFB | /* Rx interrupt on frame */
464 SDCR_BLMT | /* Little endian transmit */
465 SDCR_BLMR | /* Little endian receive */
466 SDCR_RC_MAX_RETRANS, /* Max retransmit count */
467 &regs->sdma_conf);
468 /* Port Configuration */
469 writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */
470
471 /* Set extended port configuration */
472 writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
473 PCXR_DSCP_EN | /* Enable DSCP in IP */
474 PCXR_MFL_1536 | /* Set MTU = 1536 */
475 PCXR_FLP | /* do not force link pass */
476 PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
477 &regs->pconf_ext);
478
479 update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
480
481 /* Update TX and RX queue descriptor register */
482 writel((u32)darmdfec->p_txdesc, &regs->txcdp[TXQ]);
483 writel((u32)darmdfec->p_rxdesc, &regs->rxfdp[RXQ]);
484 writel((u32)darmdfec->p_rxdesc_curr, &regs->rxcdp[RXQ]);
485
486 /* Enable Interrupts */
487 writel(ALL_INTS, &regs->im);
488
489 /* Enable Ethernet Port */
490 setbits_le32(&regs->pconf, PCR_EN);
491
492 /* Enable RX DMA engine */
493 setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
494
495#ifdef DEBUG
496 eth_dump_regs(dev);
497#endif
498
499#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
500
501#if defined(CONFIG_PHY_BASE_ADR)
502 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
503#else
504 /* Search phy address from range 0-31 */
505 phy_adr = ethernet_phy_detect(dev);
506 if (phy_adr < 0) {
507 printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
508 return -1;
509 } else {
510 debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
511 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
512 }
513#endif
514
515#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
516 /* Wait up to 5s for the link status */
517 for (i = 0; i < 5; i++) {
518 u16 phy_adr;
519
520 miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
521 /* Return if we get link up */
522 if (miiphy_link(dev->name, phy_adr))
523 return 0;
524 udelay(1000000);
525 }
526
527 printf("ARMD100 FEC: No link on %s\n", dev->name);
528 return -1;
529#endif
530#endif
531 return 0;
532}
533
534static void armdfec_halt(struct eth_device *dev)
535{
536 struct armdfec_device *darmdfec = to_darmdfec(dev);
537 struct armdfec_reg *regs = darmdfec->regs;
538
539 /* Stop RX DMA */
540 clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
541
542 /*
543 * Abort any transmit and receive operations and put DMA
544 * in idle state.
545 */
546 abortdma(dev);
547
548 /* Disable interrupts */
549 writel(0, &regs->im);
550 writel(0, &regs->ic);
551 writel(0, &regs->iwc);
552
553 /* Disable Port */
554 clrbits_le32(&regs->pconf, PCR_EN);
555}
556
557static int armdfec_send(struct eth_device *dev, volatile void *dataptr,
558 int datasize)
559{
560 struct armdfec_device *darmdfec = to_darmdfec(dev);
561 struct armdfec_reg *regs = darmdfec->regs;
562 struct tx_desc *p_txdesc = darmdfec->p_txdesc;
563 void *p = (void *)dataptr;
564 int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
565 u32 cmd_sts;
566
567 /* Copy buffer if it's misaligned */
568 if ((u32)dataptr & 0x07) {
569 if (datasize > PKTSIZE_ALIGN) {
570 printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
571 datasize);
572 return -1;
573 }
574 memcpy(darmdfec->p_aligned_txbuf, p, datasize);
575 p = darmdfec->p_aligned_txbuf;
576 }
577
578 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
579 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
580 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
581 p_txdesc->cmd_sts |= TX_EN_INT;
582 p_txdesc->buf_ptr = p;
583 p_txdesc->byte_cnt = datasize;
584
585 /* Apply send command using high priority TX queue */
586 writel((u32)p_txdesc, &regs->txcdp[TXQ]);
587 writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd);
588
589 /*
590 * wait for packet xmit completion
591 */
592 cmd_sts = readl(&p_txdesc->cmd_sts);
593 while (cmd_sts & BUF_OWNED_BY_DMA) {
594 /* return fail if error is detected */
595 if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
596 (TX_ERROR | TX_LAST_DESC)) {
597 printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
598 return -1;
599 }
600 cmd_sts = readl(&p_txdesc->cmd_sts);
601 if (!(retry--)) {
602 printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
603 __func__);
604 return -1;
605 }
606 }
607
608 return 0;
609}
610
611static int armdfec_recv(struct eth_device *dev)
612{
613 struct armdfec_device *darmdfec = to_darmdfec(dev);
614 struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
615 u32 cmd_sts;
616 u32 timeout = 0;
617
618 /* wait untill rx packet available or timeout */
619 do {
620 if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
621 timeout++;
622 } else {
623 debug("ARMD100 FEC: %s time out...\n", __func__);
624 return -1;
625 }
626 } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
627
628 if (p_rxdesc_curr->byte_cnt != 0) {
629 debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
630 "(cmd_sts= %08x)\n", __func__,
631 (u32)p_rxdesc_curr->byte_cnt,
632 (u32)p_rxdesc_curr->buf_ptr,
633 (u32)p_rxdesc_curr->cmd_sts);
634 }
635
636 /*
637 * In case received a packet without first/last bits on
638 * OR the error summary bit is on,
639 * the packets needs to be dropeed.
640 */
641 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
642
643 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
644 (RX_FIRST_DESC | RX_LAST_DESC)) {
645 printf("ARMD100 FEC: (%s) Dropping packet spread on"
646 " multiple descriptors\n", __func__);
647 } else if (cmd_sts & RX_ERROR) {
648 printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
649 __func__);
650 } else {
651 /* !!! call higher layer processing */
652 debug("ARMD100 FEC: (%s) Sending Received packet to"
653 " upper layer (NetReceive)\n", __func__);
654
655 /*
656 * let the upper layer handle the packet, subtract offset
657 * as two dummy bytes are added in received buffer see
658 * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
659 */
660 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
661 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
662 }
663 /*
664 * free these descriptors and point next in the ring
665 */
666 p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
667 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
668 p_rxdesc_curr->byte_cnt = 0;
669
670 writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr);
671
672 return 0;
673}
674
675int armada100_fec_register(unsigned long base_addr)
676{
677 struct armdfec_device *darmdfec;
678 struct eth_device *dev;
679
680 darmdfec = malloc(sizeof(struct armdfec_device));
681 if (!darmdfec)
682 goto error;
683
684 memset(darmdfec, 0, sizeof(struct armdfec_device));
685
686 darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
687 if (!darmdfec->htpr)
688 goto error1;
689
690 darmdfec->p_rxdesc = memalign(PKTALIGN,
691 ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
692
693 if (!darmdfec->p_rxdesc)
694 goto error1;
695
696 darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
697 if (!darmdfec->p_rxbuf)
698 goto error1;
699
700 darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
701 if (!darmdfec->p_aligned_txbuf)
702 goto error1;
703
704 darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
705 if (!darmdfec->p_txdesc)
706 goto error1;
707
708 dev = &darmdfec->dev;
709 /* Assign ARMADA100 Fast Ethernet Controller Base Address */
710 darmdfec->regs = (void *)base_addr;
711
712 /* must be less than NAMESIZE (16) */
713 strcpy(dev->name, "armd-fec0");
714
715 dev->init = armdfec_init;
716 dev->halt = armdfec_halt;
717 dev->send = armdfec_send;
718 dev->recv = armdfec_recv;
719
720 eth_register(dev);
721
722#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
723 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
724#endif
725 return 0;
726
727error1:
728 free(darmdfec->p_aligned_txbuf);
729 free(darmdfec->p_rxbuf);
730 free(darmdfec->p_rxdesc);
731 free(darmdfec->htpr);
732error:
733 free(darmdfec);
734 printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
735 return -1;
736}