blob: 41a3fe1a3c5eb780595a4369d6b38a391111fbff [file] [log] [blame]
Simon Glassc420ef62016-11-13 14:24:54 -07001CONFIG_ARM=y
Tom Rinia2ac2b92021-08-27 21:18:30 -04002CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +00003# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Simon Glassc420ef62016-11-13 14:24:54 -07004CONFIG_ARCH_ROCKCHIP=y
Tom Rini278b90c2018-02-03 12:10:38 -05005CONFIG_SYS_TEXT_BASE=0x00100000
Tom Rini554e5512020-08-10 15:31:07 -04006CONFIG_NR_DRAM_BANKS=1
Tom Rini2bba7802021-06-28 10:17:29 -04007CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
Tom Rinic5a6e9f2020-07-06 13:54:25 -04008CONFIG_SPL_TEXT_BASE=0xff704000
Simon Glassc420ef62016-11-13 14:24:54 -07009CONFIG_ROCKCHIP_RK3288=y
Simon Glass103c5f12021-08-08 12:20:09 -060010# CONFIG_SPL_MMC is not set
Simon Glassc420ef62016-11-13 14:24:54 -070011CONFIG_TARGET_CHROMEBOOK_MINNIE=y
Tom Rinid168bcb2019-04-29 15:54:04 -040012CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rini358b6a22018-06-04 11:57:37 -040013CONFIG_DEBUG_UART_BASE=0xff690000
14CONFIG_DEBUG_UART_CLOCK=24000000
Simon Glassc420ef62016-11-13 14:24:54 -070015CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassea2ca7e2021-08-08 12:20:14 -060016CONFIG_SPL_SPI=y
Tom Rini556fd592020-04-28 16:15:47 -040017CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rinif7d0ae92020-07-28 08:46:52 -040018CONFIG_DEBUG_UART=y
Tom Rini49c8ef02021-08-23 10:25:31 -040019CONFIG_SYS_LOAD_ADDR=0x800800
Simon Glass37304aa2019-07-20 20:51:14 -060020CONFIG_USE_PREBOOT=y
Klaus Gogera2a50532018-05-25 23:45:05 +020021CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
Tom Rini0817daa2020-10-09 12:22:06 -040022CONFIG_SILENT_CONSOLE=y
Simon Glassc420ef62016-11-13 14:24:54 -070023# CONFIG_DISPLAY_CPUINFO is not set
Mario Six78eba692018-03-28 14:38:17 +020024CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkofffdf722020-05-13 19:15:21 +000025CONFIG_BOARD_EARLY_INIT_R=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +000026# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Simon Glassc420ef62016-11-13 14:24:54 -070027CONFIG_SPL_STACK_R=y
28CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko7ba79f22019-05-13 13:51:05 +000029# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
Simon Glass1e52db62021-07-14 17:05:32 -050030# CONFIG_SPL_CRC32 is not set
Marek Vasut55500432018-04-07 16:05:27 +020031CONFIG_SPL_SPI_LOAD=y
Tom Rini3e5b62f2021-08-10 15:08:46 -040032CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rini88663122017-08-14 19:58:53 -040033CONFIG_CMD_GPIO=y
Patrick Delaunayb331cd62017-01-27 11:00:42 +010034CONFIG_CMD_GPT=y
Tom Rini88663122017-08-14 19:58:53 -040035CONFIG_CMD_I2C=y
Simon Glassc420ef62016-11-13 14:24:54 -070036CONFIG_CMD_MMC=y
Simon Glass719d36e2017-08-04 16:34:46 -060037CONFIG_CMD_SF_TEST=y
Tom Rini88663122017-08-14 19:58:53 -040038CONFIG_CMD_SPI=y
Eddie Caic3d098e2017-12-15 08:17:13 +080039CONFIG_CMD_USB=y
Simon Glassc420ef62016-11-13 14:24:54 -070040# CONFIG_CMD_SETEXPR is not set
Simon Glassc420ef62016-11-13 14:24:54 -070041CONFIG_CMD_CACHE=y
42CONFIG_CMD_TIME=y
Simon Glassec107f02019-04-26 19:03:39 -060043CONFIG_CMD_SOUND=y
Simon Glassc420ef62016-11-13 14:24:54 -070044CONFIG_CMD_PMIC=y
45CONFIG_CMD_REGULATOR=y
Patrick Delaunayb0cf7332017-01-27 11:00:37 +010046# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunaybd42a942017-01-27 11:00:41 +010047# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunayb331cd62017-01-27 11:00:42 +010048CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassc420ef62016-11-13 14:24:54 -070049CONFIG_SPL_OF_CONTROL=y
50CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Urja Rannikko7ba79f22019-05-13 13:51:05 +000051CONFIG_SPL_OF_PLATDATA=y
Tom Rini8d8ee472019-11-12 22:46:36 -050052CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Simon Glassc420ef62016-11-13 14:24:54 -070053CONFIG_REGMAP=y
54CONFIG_SPL_REGMAP=y
55CONFIG_SYSCON=y
56CONFIG_SPL_SYSCON=y
57# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko7ba79f22019-05-13 13:51:05 +000058# CONFIG_SPL_BLK is not set
Simon Glassc420ef62016-11-13 14:24:54 -070059CONFIG_CLK=y
60CONFIG_SPL_CLK=y
61CONFIG_ROCKCHIP_GPIO=y
62CONFIG_I2C_CROS_EC_TUNNEL=y
63CONFIG_SYS_I2C_ROCKCHIP=y
64CONFIG_I2C_MUX=y
65CONFIG_DM_KEYBOARD=y
66CONFIG_CROS_EC_KEYB=y
67CONFIG_CROS_EC=y
68CONFIG_CROS_EC_SPI=y
69CONFIG_PWRSEQ=y
Jaehoon Chung144d0572021-02-16 10:16:56 +090070CONFIG_MMC_PWRSEQ=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +000071# CONFIG_SPL_DM_MMC is not set
Masahiro Yamada55ed3b42017-01-10 13:32:04 +090072CONFIG_MMC_DW=y
Masahiro Yamadafed44082017-01-10 13:32:03 +090073CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal888f1842019-10-03 19:50:05 +020074CONFIG_MTD=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +000075CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay14453fb2019-02-27 15:20:36 +010076CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko64df5122019-05-13 13:51:03 +000077CONFIG_SPI_FLASH_GIGADEVICE=y
Simon Glassc420ef62016-11-13 14:24:54 -070078CONFIG_PINCTRL=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +000079CONFIG_PINCONF=y
Simon Glassc420ef62016-11-13 14:24:54 -070080CONFIG_SPL_PINCTRL=y
Urja Rannikko5e50f872020-05-13 19:15:23 +000081# CONFIG_SPL_PINCTRL_FULL is not set
Simon Glassc420ef62016-11-13 14:24:54 -070082CONFIG_DM_PMIC=y
83# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen453c5a92017-05-02 14:54:52 +080084CONFIG_PMIC_RK8XX=y
Simon Glassc420ef62016-11-13 14:24:54 -070085CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen453c5a92017-05-02 14:54:52 +080086CONFIG_REGULATOR_RK8XX=y
Simon Glassc420ef62016-11-13 14:24:54 -070087CONFIG_PWM_ROCKCHIP=y
88CONFIG_RAM=y
89CONFIG_SPL_RAM=y
Simon Glassc420ef62016-11-13 14:24:54 -070090CONFIG_DEBUG_UART_SHIFT=2
Simon Glassec107f02019-04-26 19:03:39 -060091CONFIG_SOUND=y
92CONFIG_I2S=y
93CONFIG_I2S_ROCKCHIP=y
94CONFIG_SOUND_MAX98090=y
Simon Glassc420ef62016-11-13 14:24:54 -070095CONFIG_ROCKCHIP_SPI=y
96CONFIG_SYSRESET=y
Tom Riniecad7052017-08-25 17:50:26 -040097CONFIG_USB=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +000098# CONFIG_SPL_DM_USB is not set
99CONFIG_USB_DWC2=y
Adam Ford65748642018-01-02 10:39:52 -0600100CONFIG_ROCKCHIP_USB2_PHY=y
Simon Glassc420ef62016-11-13 14:24:54 -0700101CONFIG_DM_VIDEO=y
Anatolij Gustschin8a6ffed2020-02-04 22:43:06 +0100102# CONFIG_VIDEO_BPP8 is not set
Simon Glassc420ef62016-11-13 14:24:54 -0700103CONFIG_DISPLAY=y
104CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.comb98f0a32017-04-17 22:24:23 +0800105CONFIG_DISPLAY_ROCKCHIP_EDP=y
Tom Rinifb82fe32017-06-19 09:47:40 -0400106CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassc420ef62016-11-13 14:24:54 -0700107CONFIG_CONSOLE_SCROLL_LINES=10
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000108CONFIG_SPL_TINY_MEMSET=y
Simon Glassc420ef62016-11-13 14:24:54 -0700109CONFIG_CMD_DHRYSTONE=y
110CONFIG_ERRNO_STR=y