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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenke2211742002-11-02 23:30:20 +000015#define GTREGREAD(x) 0xffffffff /* needed for debug */
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0xFFF00000
23
wdenke2211742002-11-02 23:30:20 +000024/* these hardware addresses are pretty bogus, please change them to
25 suit your needs */
26
27/* first ethernet */
28#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
29
30#define CONFIG_IPADDR 192.168.0.105
31#define CONFIG_SERVERIP 192.168.0.100
32
33#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
34
35#define CONFIG_BAUDRATE 9600 /* console baudrate */
36
37#undef CONFIG_WATCHDOG
38
39#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
40
41#define CONFIG_ZERO_BOOTDELAY_CHECK
42
43#undef CONFIG_BOOTARGS
44#define CONFIG_BOOTCOMMAND \
45 "bootp 1000000; " \
46 "setenv bootargs root=ramfs console=ttyS00,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
48 "${netmask}:${hostname}:eth0:none; " \
wdenke2211742002-11-02 23:30:20 +000049 "bootm"
50
51#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenke2211742002-11-02 23:30:20 +000053
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050054/*
55 * BOOTP options
56 */
57#define CONFIG_BOOTP_SUBNETMASK
58#define CONFIG_BOOTP_GATEWAY
59#define CONFIG_BOOTP_HOSTNAME
60#define CONFIG_BOOTP_BOOTPATH
61
62#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +000063
wdenke2211742002-11-02 23:30:20 +000064
Jon Loeligerdcaa7152007-07-07 20:56:05 -050065/*
66 * Command line configuration.
67 */
68#include <config_cmd_default.h>
69
70#define CONFIG_CMD_PCI
71#define CONFIG_CMD_JFFS2
72
wdenke2211742002-11-02 23:30:20 +000073
74/*
75 * Miscellaneous configurable options
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenke2211742002-11-02 23:30:20 +000078
79/*
80 * choose between COM1 and COM2 as serial console
81 */
82#define CONFIG_CONS_INDEX 1
83
Jon Loeligerdcaa7152007-07-07 20:56:05 -050084#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +000086#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +000088#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
90#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
91#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
94#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenke2211742002-11-02 23:30:20 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenke2211742002-11-02 23:30:20 +000099
100/*
101 * Low Level Configuration Settings
102 * (address mappings, register initial values, etc.)
103 * You should know what you are doing if you make changes here.
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_BOARD_ASM_INIT
wdenke2211742002-11-02 23:30:20 +0000106#define CONFIG_MISC_INIT_R
107
108/*
109 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#undef CONFIG_SYS_ADDRESS_MAP_A
wdenke2211742002-11-02 23:30:20 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
114#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
115#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
wdenke2211742002-11-02 23:30:20 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
118#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
119#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
wdenke2211742002-11-02 23:30:20 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
122#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
123#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
wdenke2211742002-11-02 23:30:20 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_PCI_IO_BUS 0x00800000
126#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
127#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
wdenke2211742002-11-02 23:30:20 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_ISA_IO_BUS 0x00000000
130#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
131#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
wdenke2211742002-11-02 23:30:20 +0000132
133/* driver defines FDC,IDE,... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
135#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
136#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
wdenke2211742002-11-02 23:30:20 +0000137
138/*
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenke2211742002-11-02 23:30:20 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_USR_LED_BASE 0x78000000
146#define CONFIG_SYS_NVRAM_BASE 0xff000000
147#define CONFIG_SYS_UART_BASE 0xff400000
148#define CONFIG_SYS_FLASH_BASE 0xfff00000
wdenke2211742002-11-02 23:30:20 +0000149
150#define MPC107_EUMB_ADDR 0xfce00000
151#define MPC107_EUMB_PI 0xfce41090
152#define MPC107_EUMB_GCR 0xfce41020
153#define MPC107_EUMB_IACKR 0xfce600a0
154#define MPC107_I2C_ADDR 0xfce03000
155
156/*
157 * Definitions for initial stack pointer and data area
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200160#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200161#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000163
164/*
165 * Flash mapping/organization on the MPC10x.
166 */
167#define FLASH_BASE0_PRELIM 0xff800000
168#define FLASH_BASE1_PRELIM 0xffc00000
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
171#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
174#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000175
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200176/*
177 * JFFS2 partitions
178 *
179 */
180/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100181#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200182#define CONFIG_JFFS2_DEV "nor0"
183#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
184#define CONFIG_JFFS2_PART_OFFSET 0x00000000
185
186/* mtdparts command line support */
187/* Note: fake mtd_id used, no linux mtd map file */
188/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100189#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200190#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
191#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
192*/
wdenke2211742002-11-02 23:30:20 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
195#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
196#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
197#undef CONFIG_SYS_MEMTEST
wdenke2211742002-11-02 23:30:20 +0000198
199/*
200 * Environment settings
201 */
202#define CONFIG_ENV_OVERWRITE
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200203#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
206#define CONFIG_ENV_ADDR 0x0
207#define CONFIG_ENV_MAP_ADRS 0xff000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
209#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
210#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
wdenke2211742002-11-02 23:30:20 +0000211
212/*
213 * Serial devices
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_NS16550
216#define CONFIG_SYS_NS16550_SERIAL
217#define CONFIG_SYS_NS16550_REG_SIZE 1
218#define CONFIG_SYS_NS16550_CLK 24000000
219#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0)
220#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8)
wdenke2211742002-11-02 23:30:20 +0000221
222/*
223 * PCI stuff
224 */
225#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000226#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenke2211742002-11-02 23:30:20 +0000227#define CONFIG_PCI_PNP /* pci plug-and-play */
228#define CONFIG_PCI_HOST PCI_HOST_AUTO
229#undef CONFIG_PCI_SCAN_SHOW
230
231/*
232 * Optional Video console (graphic: SMI LynxEM)
233 */
234#define CONFIG_VIDEO
235#define CONFIG_CFB_CONSOLE
236#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
Simon Glass709ea542014-07-23 06:54:59 -0600237#define VIDEO_TSTC_FCT serial_stub_tstc
238#define VIDEO_GETC_FCT serial_stub_getc
wdenke2211742002-11-02 23:30:20 +0000239
240#define CONFIG_VIDEO_SMI_LYNXEM
241#define CONFIG_VIDEO_LOGO
242#define CONFIG_CONSOLE_EXTRA_INFO
243
244/*
245 * Initial BATs
246 */
247#if 1
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_IBAT0L 0
250#define CONFIG_SYS_IBAT0U 0
251#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
252#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_IBAT1L 0
255#define CONFIG_SYS_IBAT1U 0
256#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
257#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_IBAT2L 0
260#define CONFIG_SYS_IBAT2U 0
261#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
262#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
wdenke2211742002-11-02 23:30:20 +0000263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_IBAT3L 0
265#define CONFIG_SYS_IBAT3U 0
266#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
267#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenke2211742002-11-02 23:30:20 +0000268
269#else
270
271/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
273#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
274#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
275#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000276
277/* address range for flashes */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
279#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
280#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
281#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000282
283/* ISA IO space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
285#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
286#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
287#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
wdenke2211742002-11-02 23:30:20 +0000288
289/* ISA memory space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
291#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
292#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
293#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenke2211742002-11-02 23:30:20 +0000294
295#endif
296
297/*
298 * Speed settings are board specific
299 */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200300#define CONFIG_SYS_BUS_CLK 100000000
301#define CONFIG_SYS_CPU_CLK 400000000
wdenke2211742002-11-02 23:30:20 +0000302
303/*
304 * For booting Linux, the board info and command line data
305 * have to be in the first 8 MB of memory, since this is
306 * the maximum mapped by the Linux kernel during initialization.
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000309
310/*
311 * Cache Configuration
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500314#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000316#endif
317
318/*
319 * L2CR setup -- make sure this is right for your board!
wdenk1d0350e2002-11-11 21:14:20 +0000320 * look in include/74xx_7xx.h for the defines used here
wdenke2211742002-11-02 23:30:20 +0000321 */
322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_L2
wdenke2211742002-11-02 23:30:20 +0000324
325#if 1
326#define L2_INIT 0 /* cpu 750 CXe*/
327#else
328#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000329 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000330#endif
331#define L2_ENABLE (L2_INIT | L2CR_L2E)
332
wdenke2211742002-11-02 23:30:20 +0000333#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenke2211742002-11-02 23:30:20 +0000335#define CONFIG_EEPRO100_SROM_WRITE
336
337#endif /* __CONFIG_H */