Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2019 Western Digital Corporation or its affiliates. |
| 4 | * |
| 5 | * Copyright (C) 2018 SiFive, Inc. |
| 6 | * Wesley Terpstra |
| 7 | * Paul Walmsley |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * The FU540 PRCI implements clock and reset control for the SiFive |
| 19 | * FU540-C000 chip. This driver assumes that it has sole control |
| 20 | * over all PRCI resources. |
| 21 | * |
| 22 | * This driver is based on the PRCI driver written by Wesley Terpstra. |
| 23 | * |
| 24 | * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of: |
| 25 | * https://github.com/riscv/riscv-linux |
| 26 | * |
| 27 | * References: |
| 28 | * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" |
| 29 | */ |
| 30 | |
Jagan Teki | db2f696 | 2019-05-08 19:52:18 +0530 | [diff] [blame] | 31 | #include <common.h> |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 32 | #include <asm/io.h> |
| 33 | #include <clk-uclass.h> |
| 34 | #include <clk.h> |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 35 | #include <div64.h> |
| 36 | #include <dm.h> |
| 37 | #include <errno.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 38 | #include <linux/delay.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 39 | #include <linux/err.h> |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 40 | |
| 41 | #include <linux/math64.h> |
Anup Patel | d04c79d | 2019-06-25 06:31:02 +0000 | [diff] [blame] | 42 | #include <linux/clk/analogbits-wrpll-cln28hpc.h> |
Anup Patel | 66591a7 | 2019-06-25 06:31:15 +0000 | [diff] [blame] | 43 | #include <dt-bindings/clock/sifive-fu540-prci.h> |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 44 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 45 | /* |
| 46 | * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: |
| 47 | * hfclk and rtcclk |
| 48 | */ |
| 49 | #define EXPECTED_CLK_PARENT_COUNT 2 |
| 50 | |
| 51 | /* |
| 52 | * Register offsets and bitmasks |
| 53 | */ |
| 54 | |
| 55 | /* COREPLLCFG0 */ |
| 56 | #define PRCI_COREPLLCFG0_OFFSET 0x4 |
| 57 | #define PRCI_COREPLLCFG0_DIVR_SHIFT 0 |
| 58 | #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) |
| 59 | #define PRCI_COREPLLCFG0_DIVF_SHIFT 6 |
| 60 | #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) |
| 61 | #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 |
| 62 | #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) |
| 63 | #define PRCI_COREPLLCFG0_RANGE_SHIFT 18 |
| 64 | #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) |
| 65 | #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 |
| 66 | #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) |
| 67 | #define PRCI_COREPLLCFG0_FSE_SHIFT 25 |
| 68 | #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) |
| 69 | #define PRCI_COREPLLCFG0_LOCK_SHIFT 31 |
| 70 | #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) |
| 71 | |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 72 | /* COREPLLCFG1 */ |
| 73 | #define PRCI_COREPLLCFG1_OFFSET 0x8 |
| 74 | #define PRCI_COREPLLCFG1_CKE_SHIFT 31 |
| 75 | #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) |
| 76 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 77 | /* DDRPLLCFG0 */ |
| 78 | #define PRCI_DDRPLLCFG0_OFFSET 0xc |
| 79 | #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 |
| 80 | #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) |
| 81 | #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 |
| 82 | #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) |
| 83 | #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 |
| 84 | #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) |
| 85 | #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 |
| 86 | #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) |
| 87 | #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 |
| 88 | #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) |
| 89 | #define PRCI_DDRPLLCFG0_FSE_SHIFT 25 |
| 90 | #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) |
| 91 | #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 |
| 92 | #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) |
| 93 | |
| 94 | /* DDRPLLCFG1 */ |
| 95 | #define PRCI_DDRPLLCFG1_OFFSET 0x10 |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 96 | #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 97 | #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) |
| 98 | |
| 99 | /* GEMGXLPLLCFG0 */ |
| 100 | #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c |
| 101 | #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 |
| 102 | #define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ |
| 103 | (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) |
| 104 | #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 |
| 105 | #define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ |
| 106 | (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) |
| 107 | #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 |
| 108 | #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) |
| 109 | #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 |
| 110 | #define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ |
| 111 | (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) |
| 112 | #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 |
| 113 | #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ |
| 114 | (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) |
| 115 | #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 |
| 116 | #define PRCI_GEMGXLPLLCFG0_FSE_MASK \ |
| 117 | (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) |
| 118 | #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 |
| 119 | #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) |
| 120 | |
| 121 | /* GEMGXLPLLCFG1 */ |
| 122 | #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 123 | #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 124 | #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) |
| 125 | |
| 126 | /* CORECLKSEL */ |
| 127 | #define PRCI_CORECLKSEL_OFFSET 0x24 |
| 128 | #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 |
| 129 | #define PRCI_CORECLKSEL_CORECLKSEL_MASK \ |
| 130 | (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) |
| 131 | |
| 132 | /* DEVICESRESETREG */ |
| 133 | #define PRCI_DEVICESRESETREG_OFFSET 0x28 |
| 134 | #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 |
| 135 | #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ |
| 136 | (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) |
| 137 | #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 |
| 138 | #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ |
| 139 | (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) |
| 140 | #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 |
| 141 | #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ |
| 142 | (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) |
| 143 | #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 |
| 144 | #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ |
| 145 | (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) |
| 146 | #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 |
| 147 | #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ |
| 148 | (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) |
| 149 | |
| 150 | /* CLKMUXSTATUSREG */ |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 151 | #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 152 | #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 |
| 153 | #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ |
| 154 | (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) |
| 155 | |
| 156 | /* |
| 157 | * Private structures |
| 158 | */ |
| 159 | |
| 160 | /** |
| 161 | * struct __prci_data - per-device-instance data |
| 162 | * @va: base virtual address of the PRCI IP block |
| 163 | * @parent: parent clk instance |
| 164 | * |
| 165 | * PRCI per-device instance data |
| 166 | */ |
| 167 | struct __prci_data { |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 168 | void *va; |
| 169 | struct clk parent_hfclk; |
| 170 | struct clk parent_rtcclk; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | /** |
| 174 | * struct __prci_wrpll_data - WRPLL configuration and integration data |
| 175 | * @c: WRPLL current configuration record |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 176 | * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) |
| 177 | * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 178 | * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 179 | * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 180 | * |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 181 | * @enable_bypass and @disable_bypass are used for WRPLL instances |
| 182 | * that contain a separate external glitchless clock mux downstream |
| 183 | * from the PLL. The WRPLL internal bypass mux is not glitchless. |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 184 | */ |
| 185 | struct __prci_wrpll_data { |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 186 | struct wrpll_cfg c; |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 187 | void (*enable_bypass)(struct __prci_data *pd); |
| 188 | void (*disable_bypass)(struct __prci_data *pd); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 189 | u8 cfg0_offs; |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 190 | u8 cfg1_offs; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | struct __prci_clock; |
| 194 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 195 | /* struct __prci_clock_ops - clock operations */ |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 196 | struct __prci_clock_ops { |
| 197 | int (*set_rate)(struct __prci_clock *pc, |
| 198 | unsigned long rate, |
| 199 | unsigned long parent_rate); |
| 200 | unsigned long (*round_rate)(struct __prci_clock *pc, |
| 201 | unsigned long rate, |
| 202 | unsigned long *parent_rate); |
| 203 | unsigned long (*recalc_rate)(struct __prci_clock *pc, |
| 204 | unsigned long parent_rate); |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 205 | int (*enable_clk)(struct __prci_clock *pc, bool enable); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | /** |
| 209 | * struct __prci_clock - describes a clock device managed by PRCI |
| 210 | * @name: user-readable clock name string - should match the manual |
| 211 | * @parent_name: parent name for this clock |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 212 | * @ops: struct __prci_clock_ops for control |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 213 | * @pwd: WRPLL-specific data, associated with this clock (if not NULL) |
| 214 | * @pd: PRCI-specific data associated with this clock (if not NULL) |
| 215 | * |
| 216 | * PRCI clock data. Used by the PRCI driver to register PRCI-provided |
| 217 | * clocks to the Linux clock infrastructure. |
| 218 | */ |
| 219 | struct __prci_clock { |
| 220 | const char *name; |
| 221 | const char *parent_name; |
| 222 | const struct __prci_clock_ops *ops; |
| 223 | struct __prci_wrpll_data *pwd; |
| 224 | struct __prci_data *pd; |
| 225 | }; |
| 226 | |
| 227 | /* |
| 228 | * Private functions |
| 229 | */ |
| 230 | |
| 231 | /** |
| 232 | * __prci_readl() - read from a PRCI register |
| 233 | * @pd: PRCI context |
| 234 | * @offs: register offset to read from (in bytes, from PRCI base address) |
| 235 | * |
| 236 | * Read the register located at offset @offs from the base virtual |
| 237 | * address of the PRCI register target described by @pd, and return |
| 238 | * the value to the caller. |
| 239 | * |
| 240 | * Context: Any context. |
| 241 | * |
| 242 | * Return: the contents of the register described by @pd and @offs. |
| 243 | */ |
| 244 | static u32 __prci_readl(struct __prci_data *pd, u32 offs) |
| 245 | { |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 246 | return readl(pd->va + offs); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) |
| 250 | { |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 251 | writel(v, pd->va + offs); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | /* WRPLL-related private functions */ |
| 255 | |
| 256 | /** |
| 257 | * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 258 | * @c: ptr to a struct wrpll_cfg record to write config into |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 259 | * @r: value read from the PRCI PLL configuration register |
| 260 | * |
| 261 | * Given a value @r read from an FU540 PRCI PLL configuration register, |
| 262 | * split it into fields and populate it into the WRPLL configuration record |
| 263 | * pointed to by @c. |
| 264 | * |
| 265 | * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros |
| 266 | * have the same register layout. |
| 267 | * |
| 268 | * Context: Any context. |
| 269 | */ |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 270 | static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 271 | { |
| 272 | u32 v; |
| 273 | |
| 274 | v = r & PRCI_COREPLLCFG0_DIVR_MASK; |
| 275 | v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; |
| 276 | c->divr = v; |
| 277 | |
| 278 | v = r & PRCI_COREPLLCFG0_DIVF_MASK; |
| 279 | v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; |
| 280 | c->divf = v; |
| 281 | |
| 282 | v = r & PRCI_COREPLLCFG0_DIVQ_MASK; |
| 283 | v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; |
| 284 | c->divq = v; |
| 285 | |
| 286 | v = r & PRCI_COREPLLCFG0_RANGE_MASK; |
| 287 | v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; |
| 288 | c->range = v; |
| 289 | |
| 290 | c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | |
| 291 | WRPLL_FLAGS_EXT_FEEDBACK_MASK); |
| 292 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 293 | /* external feedback mode not supported */ |
| 294 | c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | /** |
| 298 | * __prci_wrpll_pack() - pack PLL configuration parameters into a register value |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 299 | * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 300 | * |
| 301 | * Using a set of WRPLL configuration values pointed to by @c, |
| 302 | * assemble a PRCI PLL configuration register value, and return it to |
| 303 | * the caller. |
| 304 | * |
| 305 | * Context: Any context. Caller must ensure that the contents of the |
| 306 | * record pointed to by @c do not change during the execution |
| 307 | * of this function. |
| 308 | * |
| 309 | * Returns: a value suitable for writing into a PRCI PLL configuration |
| 310 | * register |
| 311 | */ |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 312 | static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 313 | { |
| 314 | u32 r = 0; |
| 315 | |
| 316 | r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; |
| 317 | r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; |
| 318 | r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; |
| 319 | r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 320 | |
| 321 | /* external feedback mode not supported */ |
| 322 | r |= PRCI_COREPLLCFG0_FSE_MASK; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 323 | |
| 324 | return r; |
| 325 | } |
| 326 | |
| 327 | /** |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 328 | * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 329 | * @pd: PRCI context |
| 330 | * @pwd: PRCI WRPLL metadata |
| 331 | * |
| 332 | * Read the current configuration of the PLL identified by @pwd from |
| 333 | * the PRCI identified by @pd, and store it into the local configuration |
| 334 | * cache in @pwd. |
| 335 | * |
| 336 | * Context: Any context. Caller must prevent the records pointed to by |
| 337 | * @pd and @pwd from changing during execution. |
| 338 | */ |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 339 | static void __prci_wrpll_read_cfg0(struct __prci_data *pd, |
| 340 | struct __prci_wrpll_data *pwd) |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 341 | { |
| 342 | __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); |
| 343 | } |
| 344 | |
| 345 | /** |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 346 | * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 347 | * @pd: PRCI context |
| 348 | * @pwd: PRCI WRPLL metadata |
| 349 | * @c: WRPLL configuration record to write |
| 350 | * |
| 351 | * Write the WRPLL configuration described by @c into the WRPLL |
| 352 | * configuration register identified by @pwd in the PRCI instance |
| 353 | * described by @c. Make a cached copy of the WRPLL's current |
| 354 | * configuration so it can be used by other code. |
| 355 | * |
| 356 | * Context: Any context. Caller must prevent the records pointed to by |
| 357 | * @pd and @pwd from changing during execution. |
| 358 | */ |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 359 | static void __prci_wrpll_write_cfg0(struct __prci_data *pd, |
| 360 | struct __prci_wrpll_data *pwd, |
| 361 | struct wrpll_cfg *c) |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 362 | { |
| 363 | __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); |
| 364 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 365 | memcpy(&pwd->c, c, sizeof(*c)); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 366 | } |
| 367 | |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 368 | /** |
| 369 | * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration |
| 370 | * into the PRCI |
| 371 | * @pd: PRCI context |
| 372 | * @pwd: PRCI WRPLL metadata |
| 373 | * @enable: Clock enable or disable value |
| 374 | */ |
| 375 | static void __prci_wrpll_write_cfg1(struct __prci_data *pd, |
| 376 | struct __prci_wrpll_data *pwd, |
| 377 | u32 enable) |
| 378 | { |
| 379 | __prci_writel(enable, pwd->cfg1_offs, pd); |
| 380 | } |
| 381 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 382 | /* Core clock mux control */ |
| 383 | |
| 384 | /** |
| 385 | * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK |
| 386 | * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg |
| 387 | * |
| 388 | * Switch the CORECLK mux to the HFCLK input source; return once complete. |
| 389 | * |
| 390 | * Context: Any context. Caller must prevent concurrent changes to the |
| 391 | * PRCI_CORECLKSEL_OFFSET register. |
| 392 | */ |
| 393 | static void __prci_coreclksel_use_hfclk(struct __prci_data *pd) |
| 394 | { |
| 395 | u32 r; |
| 396 | |
| 397 | r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); |
| 398 | r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; |
| 399 | __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); |
| 400 | |
| 401 | r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ |
| 402 | } |
| 403 | |
| 404 | /** |
| 405 | * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL |
| 406 | * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg |
| 407 | * |
| 408 | * Switch the CORECLK mux to the PLL output clock; return once complete. |
| 409 | * |
| 410 | * Context: Any context. Caller must prevent concurrent changes to the |
| 411 | * PRCI_CORECLKSEL_OFFSET register. |
| 412 | */ |
| 413 | static void __prci_coreclksel_use_corepll(struct __prci_data *pd) |
| 414 | { |
| 415 | u32 r; |
| 416 | |
| 417 | r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); |
| 418 | r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; |
| 419 | __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); |
| 420 | |
| 421 | r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ |
| 422 | } |
| 423 | |
| 424 | static unsigned long sifive_fu540_prci_wrpll_recalc_rate( |
| 425 | struct __prci_clock *pc, |
| 426 | unsigned long parent_rate) |
| 427 | { |
| 428 | struct __prci_wrpll_data *pwd = pc->pwd; |
| 429 | |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 430 | return wrpll_calc_output_rate(&pwd->c, parent_rate); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | static unsigned long sifive_fu540_prci_wrpll_round_rate( |
| 434 | struct __prci_clock *pc, |
| 435 | unsigned long rate, |
| 436 | unsigned long *parent_rate) |
| 437 | { |
| 438 | struct __prci_wrpll_data *pwd = pc->pwd; |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 439 | struct wrpll_cfg c; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 440 | |
| 441 | memcpy(&c, &pwd->c, sizeof(c)); |
| 442 | |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 443 | wrpll_configure_for_rate(&c, rate, *parent_rate); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 444 | |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 445 | return wrpll_calc_output_rate(&c, *parent_rate); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc, |
| 449 | unsigned long rate, |
| 450 | unsigned long parent_rate) |
| 451 | { |
| 452 | struct __prci_wrpll_data *pwd = pc->pwd; |
| 453 | struct __prci_data *pd = pc->pd; |
| 454 | int r; |
| 455 | |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 456 | r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 457 | if (r) |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 458 | return r; |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 459 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 460 | if (pwd->enable_bypass) |
| 461 | pwd->enable_bypass(pd); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 462 | |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 463 | __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 464 | |
Anup Patel | c236802 | 2019-06-25 06:31:08 +0000 | [diff] [blame] | 465 | udelay(wrpll_calc_max_lock_us(&pwd->c)); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 466 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 467 | if (pwd->disable_bypass) |
| 468 | pwd->disable_bypass(pd); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 473 | static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable) |
| 474 | { |
| 475 | struct __prci_wrpll_data *pwd = pc->pwd; |
| 476 | struct __prci_data *pd = pc->pd; |
| 477 | |
| 478 | if (enable) { |
| 479 | __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); |
| 480 | } else { |
| 481 | u32 r; |
| 482 | |
| 483 | r = __prci_readl(pd, pwd->cfg1_offs); |
| 484 | r &= ~PRCI_COREPLLCFG1_CKE_MASK; |
| 485 | |
| 486 | __prci_wrpll_write_cfg1(pd, pwd, r); |
| 487 | } |
| 488 | |
| 489 | return 0; |
| 490 | } |
| 491 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 492 | static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { |
| 493 | .set_rate = sifive_fu540_prci_wrpll_set_rate, |
| 494 | .round_rate = sifive_fu540_prci_wrpll_round_rate, |
| 495 | .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 496 | .enable_clk = sifive_fu540_prci_clock_enable, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 497 | }; |
| 498 | |
| 499 | static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = { |
| 500 | .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 501 | .enable_clk = sifive_fu540_prci_clock_enable, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 502 | }; |
| 503 | |
| 504 | /* TLCLKSEL clock integration */ |
| 505 | |
| 506 | static unsigned long sifive_fu540_prci_tlclksel_recalc_rate( |
| 507 | struct __prci_clock *pc, |
| 508 | unsigned long parent_rate) |
| 509 | { |
| 510 | struct __prci_data *pd = pc->pd; |
| 511 | u32 v; |
| 512 | u8 div; |
| 513 | |
| 514 | v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); |
| 515 | v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; |
| 516 | div = v ? 1 : 2; |
| 517 | |
| 518 | return div_u64(parent_rate, div); |
| 519 | } |
| 520 | |
| 521 | static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { |
| 522 | .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, |
| 523 | }; |
| 524 | |
| 525 | /* |
| 526 | * PRCI integration data for each WRPLL instance |
| 527 | */ |
| 528 | |
| 529 | static struct __prci_wrpll_data __prci_corepll_data = { |
| 530 | .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 531 | .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 532 | .enable_bypass = __prci_coreclksel_use_hfclk, |
| 533 | .disable_bypass = __prci_coreclksel_use_corepll, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | static struct __prci_wrpll_data __prci_ddrpll_data = { |
| 537 | .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 538 | .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 539 | }; |
| 540 | |
| 541 | static struct __prci_wrpll_data __prci_gemgxlpll_data = { |
| 542 | .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 543 | .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 544 | }; |
| 545 | |
| 546 | /* |
| 547 | * List of clock controls provided by the PRCI |
| 548 | */ |
| 549 | |
| 550 | static struct __prci_clock __prci_init_clocks[] = { |
| 551 | [PRCI_CLK_COREPLL] = { |
| 552 | .name = "corepll", |
| 553 | .parent_name = "hfclk", |
| 554 | .ops = &sifive_fu540_prci_wrpll_clk_ops, |
| 555 | .pwd = &__prci_corepll_data, |
| 556 | }, |
| 557 | [PRCI_CLK_DDRPLL] = { |
| 558 | .name = "ddrpll", |
| 559 | .parent_name = "hfclk", |
| 560 | .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, |
| 561 | .pwd = &__prci_ddrpll_data, |
| 562 | }, |
| 563 | [PRCI_CLK_GEMGXLPLL] = { |
| 564 | .name = "gemgxlpll", |
| 565 | .parent_name = "hfclk", |
| 566 | .ops = &sifive_fu540_prci_wrpll_clk_ops, |
| 567 | .pwd = &__prci_gemgxlpll_data, |
| 568 | }, |
| 569 | [PRCI_CLK_TLCLK] = { |
| 570 | .name = "tlclk", |
| 571 | .parent_name = "corepll", |
| 572 | .ops = &sifive_fu540_prci_tlclksel_clk_ops, |
| 573 | }, |
| 574 | }; |
| 575 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 576 | static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc) |
| 577 | { |
| 578 | ulong parent_rate; |
| 579 | struct __prci_clock *p; |
| 580 | |
| 581 | if (strcmp(pc->parent_name, "corepll") == 0) { |
| 582 | p = &__prci_init_clocks[PRCI_CLK_COREPLL]; |
| 583 | if (!p->pd || !p->ops->recalc_rate) |
| 584 | return -ENXIO; |
| 585 | |
| 586 | return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p)); |
| 587 | } |
| 588 | |
| 589 | if (strcmp(pc->parent_name, "rtcclk") == 0) |
| 590 | parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); |
| 591 | else |
| 592 | parent_rate = clk_get_rate(&pc->pd->parent_hfclk); |
| 593 | |
| 594 | return parent_rate; |
| 595 | } |
| 596 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 597 | static ulong sifive_fu540_prci_get_rate(struct clk *clk) |
| 598 | { |
| 599 | struct __prci_clock *pc; |
| 600 | |
| 601 | if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) |
| 602 | return -ENXIO; |
| 603 | |
| 604 | pc = &__prci_init_clocks[clk->id]; |
| 605 | if (!pc->pd || !pc->ops->recalc_rate) |
| 606 | return -ENXIO; |
| 607 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 608 | return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc)); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) |
| 612 | { |
| 613 | int err; |
| 614 | struct __prci_clock *pc; |
| 615 | |
| 616 | if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) |
| 617 | return -ENXIO; |
| 618 | |
| 619 | pc = &__prci_init_clocks[clk->id]; |
| 620 | if (!pc->pd || !pc->ops->set_rate) |
| 621 | return -ENXIO; |
| 622 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 623 | err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc)); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 624 | if (err) |
| 625 | return err; |
| 626 | |
| 627 | return rate; |
| 628 | } |
| 629 | |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 630 | static int sifive_fu540_prci_enable(struct clk *clk) |
| 631 | { |
| 632 | struct __prci_clock *pc; |
| 633 | int ret = 0; |
| 634 | |
| 635 | if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) |
| 636 | return -ENXIO; |
| 637 | |
| 638 | pc = &__prci_init_clocks[clk->id]; |
| 639 | if (!pc->pd) |
| 640 | return -ENXIO; |
| 641 | |
| 642 | if (pc->ops->enable_clk) |
| 643 | ret = pc->ops->enable_clk(pc, 1); |
| 644 | |
| 645 | return ret; |
| 646 | } |
| 647 | |
| 648 | static int sifive_fu540_prci_disable(struct clk *clk) |
| 649 | { |
| 650 | struct __prci_clock *pc; |
| 651 | int ret = 0; |
| 652 | |
| 653 | if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) |
| 654 | return -ENXIO; |
| 655 | |
| 656 | pc = &__prci_init_clocks[clk->id]; |
| 657 | if (!pc->pd) |
| 658 | return -ENXIO; |
| 659 | |
| 660 | if (pc->ops->enable_clk) |
| 661 | ret = pc->ops->enable_clk(pc, 0); |
| 662 | |
| 663 | return ret; |
| 664 | } |
| 665 | |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 666 | static int sifive_fu540_prci_probe(struct udevice *dev) |
| 667 | { |
| 668 | int i, err; |
| 669 | struct __prci_clock *pc; |
| 670 | struct __prci_data *pd = dev_get_priv(dev); |
| 671 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 672 | pd->va = (void *)dev_read_addr(dev); |
| 673 | if (IS_ERR(pd->va)) |
| 674 | return PTR_ERR(pd->va); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 675 | |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 676 | err = clk_get_by_index(dev, 0, &pd->parent_hfclk); |
| 677 | if (err) |
| 678 | return err; |
| 679 | |
| 680 | err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 681 | if (err) |
| 682 | return err; |
| 683 | |
| 684 | for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) { |
| 685 | pc = &__prci_init_clocks[i]; |
| 686 | pc->pd = pd; |
| 687 | if (pc->pwd) |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 688 | __prci_wrpll_read_cfg0(pd, pc->pwd); |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 689 | } |
| 690 | |
| 691 | return 0; |
| 692 | } |
| 693 | |
| 694 | static struct clk_ops sifive_fu540_prci_ops = { |
| 695 | .set_rate = sifive_fu540_prci_set_rate, |
| 696 | .get_rate = sifive_fu540_prci_get_rate, |
Pragnesh Patel | 79e49b0 | 2020-05-29 11:33:29 +0530 | [diff] [blame^] | 697 | .enable = sifive_fu540_prci_enable, |
| 698 | .disable = sifive_fu540_prci_disable, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 699 | }; |
| 700 | |
| 701 | static const struct udevice_id sifive_fu540_prci_ids[] = { |
Anup Patel | ed0ef37 | 2019-06-25 06:31:21 +0000 | [diff] [blame] | 702 | { .compatible = "sifive,fu540-c000-prci" }, |
Anup Patel | c40b6df | 2019-02-25 08:14:49 +0000 | [diff] [blame] | 703 | { } |
| 704 | }; |
| 705 | |
| 706 | U_BOOT_DRIVER(sifive_fu540_prci) = { |
| 707 | .name = "sifive-fu540-prci", |
| 708 | .id = UCLASS_CLK, |
| 709 | .of_match = sifive_fu540_prci_ids, |
| 710 | .probe = sifive_fu540_prci_probe, |
| 711 | .ops = &sifive_fu540_prci_ops, |
| 712 | .priv_auto_alloc_size = sizeof(struct __prci_data), |
| 713 | }; |