Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 4 | */ |
Dinh Nguyen | 48275c9 | 2015-12-03 16:05:59 -0600 | [diff] [blame] | 5 | #ifndef __CONFIG_SOCFPGA_COMMON_H__ |
| 6 | #define __CONFIG_SOCFPGA_COMMON_H__ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 7 | |
Simon Glass | 1af3c7f | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 8 | #include <linux/stringify.h> |
| 9 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 10 | /* |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | * Memory configurations |
| 12 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 13 | #define PHYS_SDRAM_1 0x0 |
Ley Foon Tan | 1b25940 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 14 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 15 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
Ley Foon Tan | 4f17f29 | 2020-03-06 16:55:19 +0800 | [diff] [blame] | 16 | #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE |
Ley Foon Tan | 53b5929 | 2020-12-22 09:53:25 +0800 | [diff] [blame] | 17 | #define CONFIG_SPL_PAD_TO 0x10000 |
Ley Foon Tan | 1b25940 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 18 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
| 19 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 |
Ley Foon Tan | 53b5929 | 2020-12-22 09:53:25 +0800 | [diff] [blame] | 20 | #define CONFIG_SPL_PAD_TO 0x40000 |
Simon Goldschmidt | 4399e48 | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 21 | /* SPL memory allocation configuration, this is for FAT implementation */ |
| 22 | #ifndef CONFIG_SYS_SPL_MALLOC_SIZE |
| 23 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 |
| 24 | #endif |
Ley Foon Tan | 4f17f29 | 2020-03-06 16:55:19 +0800 | [diff] [blame] | 25 | #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ |
| 26 | CONFIG_SYS_SPL_MALLOC_SIZE) |
Simon Goldschmidt | 4399e48 | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 28 | CONFIG_SYS_INIT_RAM_SIZE) |
Ley Foon Tan | 1b25940 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 29 | #endif |
Stefan Roese | f457c52 | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal |
| 33 | * SRAM as bootcounter storage. Make sure to not put the stack directly |
| 34 | * at this address to not overwrite the bootcounter by checking, if the |
| 35 | * bootcounter address is located in the internal SRAM. |
| 36 | */ |
| 37 | #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ |
| 38 | (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 39 | CONFIG_SYS_INIT_RAM_SIZE))) |
Simon Goldschmidt | 4399e48 | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 40 | #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR |
Stefan Roese | f457c52 | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 41 | #else |
Simon Goldschmidt | 4399e48 | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 42 | #define CONFIG_SPL_STACK \ |
Marek Vasut | 768f23d | 2018-04-26 22:23:05 +0200 | [diff] [blame] | 43 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
Stefan Roese | f457c52 | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 44 | #endif |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 45 | |
Simon Goldschmidt | 4399e48 | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 46 | /* |
| 47 | * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc |
| 48 | * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage |
| 49 | * in U-Boot pre-reloc is higher than in SPL. |
| 50 | */ |
| 51 | #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR |
| 52 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR |
| 53 | #else |
| 54 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK |
| 55 | #endif |
| 56 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 58 | |
| 59 | /* |
| 60 | * U-Boot general configurations |
| 61 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 62 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 63 | /* Print buffer size */ |
| 64 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ |
| 65 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 66 | /* Boot argument buffer size */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Cache |
| 70 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_L2_PL310 |
| 72 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS |
| 73 | |
| 74 | /* |
| 75 | * Ethernet on SoC (EMAC) |
| 76 | */ |
Marek Vasut | f791732 | 2018-04-23 01:26:10 +0200 | [diff] [blame] | 77 | #ifdef CONFIG_CMD_NET |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 78 | #define CONFIG_DW_ALTDESCRIPTOR |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 79 | #endif |
| 80 | |
| 81 | /* |
| 82 | * FPGA Driver |
| 83 | */ |
| 84 | #ifdef CONFIG_CMD_FPGA |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 85 | #define CONFIG_FPGA_COUNT 1 |
| 86 | #endif |
Tien Fong Chee | 9af91b7 | 2017-07-26 13:05:44 +0800 | [diff] [blame] | 87 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 88 | /* |
| 89 | * L4 OSC1 Timer 0 |
| 90 | */ |
Marek Vasut | 331c372 | 2018-08-18 16:00:31 +0200 | [diff] [blame] | 91 | #ifndef CONFIG_TIMER |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
| 93 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
| 94 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
Marek Vasut | c808ab4 | 2020-02-15 14:10:02 +0100 | [diff] [blame] | 95 | #ifndef CONFIG_SYS_TIMER_RATE |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 96 | #define CONFIG_SYS_TIMER_RATE 25000000 |
Marek Vasut | 331c372 | 2018-08-18 16:00:31 +0200 | [diff] [blame] | 97 | #endif |
Marek Vasut | c808ab4 | 2020-02-15 14:10:02 +0100 | [diff] [blame] | 98 | #endif |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 99 | |
| 100 | /* |
| 101 | * L4 Watchdog |
| 102 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 103 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
| 104 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 105 | |
| 106 | /* |
| 107 | * MMC Driver |
| 108 | */ |
| 109 | #ifdef CONFIG_CMD_MMC |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 110 | /* FIXME */ |
| 111 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ |
| 112 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ |
| 113 | #endif |
| 114 | |
Stefan Roese | 7fb0f59 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 115 | /* |
Marek Vasut | c339ea5 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 116 | * NAND Support |
| 117 | */ |
| 118 | #ifdef CONFIG_NAND_DENALI |
| 119 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Marek Vasut | c339ea5 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 120 | #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS |
| 121 | #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS |
Marek Vasut | c339ea5 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 122 | #endif |
| 123 | |
| 124 | /* |
Stefan Roese | 7fb0f59 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 125 | * QSPI support |
| 126 | */ |
Stefan Roese | 7fb0f59 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 127 | /* QSPI reference clock */ |
| 128 | #ifndef __ASSEMBLY__ |
| 129 | unsigned int cm_get_qspi_controller_clk_hz(void); |
| 130 | #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() |
| 131 | #endif |
Stefan Roese | 7fb0f59 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 132 | |
Marek Vasut | 0c745d0 | 2015-08-19 23:23:53 +0200 | [diff] [blame] | 133 | /* |
Marek Vasut | 20cadbb | 2014-10-24 23:34:25 +0200 | [diff] [blame] | 134 | * USB |
| 135 | */ |
Marek Vasut | 20cadbb | 2014-10-24 23:34:25 +0200 | [diff] [blame] | 136 | |
| 137 | /* |
Marek Vasut | 0223a95 | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 138 | * USB Gadget (DFU, UMS) |
| 139 | */ |
| 140 | #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) |
Marek Vasut | 0223a95 | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 141 | #define DFU_DEFAULT_POLL_TIMEOUT 300 |
| 142 | |
| 143 | /* USB IDs */ |
Sam Protsenko | e6c0bc0 | 2016-04-13 14:20:30 +0300 | [diff] [blame] | 144 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 |
| 145 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 |
Marek Vasut | 0223a95 | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 146 | #endif |
| 147 | |
| 148 | /* |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 149 | * U-Boot environment |
| 150 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 151 | |
Chin Liang See | 79cc48e | 2015-12-21 21:02:45 +0800 | [diff] [blame] | 152 | /* Environment for SDMMC boot */ |
Chin Liang See | 79cc48e | 2015-12-21 21:02:45 +0800 | [diff] [blame] | 153 | |
Chin Liang See | ec8b752 | 2016-02-24 16:50:22 +0800 | [diff] [blame] | 154 | /* Environment for QSPI boot */ |
Chin Liang See | ec8b752 | 2016-02-24 16:50:22 +0800 | [diff] [blame] | 155 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 156 | /* |
| 157 | * SPL |
Marek Vasut | 34584d1 | 2014-10-16 12:25:40 +0200 | [diff] [blame] | 158 | * |
Tien Fong Chee | 421a21c | 2017-12-05 15:58:04 +0800 | [diff] [blame] | 159 | * SRAM Memory layout for gen 5: |
Marek Vasut | 34584d1 | 2014-10-16 12:25:40 +0200 | [diff] [blame] | 160 | * |
| 161 | * 0xFFFF_0000 ...... Start of SRAM |
| 162 | * 0xFFFF_xxxx ...... Top of stack (grows down) |
Simon Goldschmidt | 798baf7 | 2019-04-09 21:02:03 +0200 | [diff] [blame] | 163 | * 0xFFFF_yyyy ...... Global Data |
| 164 | * 0xFFFF_zzzz ...... Malloc area |
| 165 | * 0xFFFF_FFFF ...... End of SRAM |
Tien Fong Chee | 421a21c | 2017-12-05 15:58:04 +0800 | [diff] [blame] | 166 | * |
| 167 | * SRAM Memory layout for Arria 10: |
| 168 | * 0xFFE0_0000 ...... Start of SRAM (bottom) |
| 169 | * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) |
| 170 | * 0xFFEy_yyyy ...... Global Data |
| 171 | * 0xFFEz_zzzz ...... Malloc area (grows up to top) |
| 172 | * 0xFFE3_FFFF ...... End of SRAM (top) |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 173 | */ |
Simon Goldschmidt | 92a4745 | 2019-03-15 20:44:32 +0100 | [diff] [blame] | 174 | #ifndef CONFIG_SPL_TEXT_BASE |
Ley Foon Tan | 1b25940 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 175 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE |
Simon Goldschmidt | 92a4745 | 2019-03-15 20:44:32 +0100 | [diff] [blame] | 176 | #endif |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 177 | |
Marek Vasut | d3f34e7 | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 178 | /* SPL SDMMC boot support */ |
Simon Glass | 103c5f1 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 179 | #ifdef CONFIG_SPL_MMC |
Tien Fong Chee | f4b4092 | 2019-01-23 14:20:05 +0800 | [diff] [blame] | 180 | #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) |
Dalon Westergreen | 998f7cb | 2019-08-07 10:37:36 -0700 | [diff] [blame] | 181 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 182 | #endif |
Marek Vasut | d3f34e7 | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 183 | #endif |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 184 | |
Marek Vasut | 346d6f5 | 2015-07-21 07:50:03 +0200 | [diff] [blame] | 185 | /* SPL QSPI boot support */ |
Marek Vasut | 346d6f5 | 2015-07-21 07:50:03 +0200 | [diff] [blame] | 186 | |
Marek Vasut | c339ea5 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 187 | /* SPL NAND boot support */ |
Marek Vasut | c339ea5 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 188 | |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 189 | /* Extra Environment */ |
| 190 | #ifndef CONFIG_SPL_BUILD |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 191 | |
Simon Goldschmidt | 1c7fa79 | 2018-01-25 07:18:27 +0100 | [diff] [blame] | 192 | #ifdef CONFIG_CMD_DHCP |
| 193 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) |
| 194 | #else |
| 195 | #define BOOT_TARGET_DEVICES_DHCP(func) |
| 196 | #endif |
| 197 | |
Joe Hershberger | 86271b3 | 2018-04-13 15:26:40 -0500 | [diff] [blame] | 198 | #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 199 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) |
| 200 | #else |
| 201 | #define BOOT_TARGET_DEVICES_PXE(func) |
| 202 | #endif |
| 203 | |
| 204 | #ifdef CONFIG_CMD_MMC |
| 205 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
| 206 | #else |
| 207 | #define BOOT_TARGET_DEVICES_MMC(func) |
| 208 | #endif |
| 209 | |
| 210 | #define BOOT_TARGET_DEVICES(func) \ |
| 211 | BOOT_TARGET_DEVICES_MMC(func) \ |
| 212 | BOOT_TARGET_DEVICES_PXE(func) \ |
Simon Goldschmidt | 1c7fa79 | 2018-01-25 07:18:27 +0100 | [diff] [blame] | 213 | BOOT_TARGET_DEVICES_DHCP(func) |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 214 | |
| 215 | #include <config_distro_bootcmd.h> |
| 216 | |
| 217 | #ifndef CONFIG_EXTRA_ENV_SETTINGS |
| 218 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 219 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| 220 | "bootm_size=0xa000000\0" \ |
| 221 | "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ |
| 222 | "fdt_addr_r=0x02000000\0" \ |
| 223 | "scriptaddr=0x02100000\0" \ |
| 224 | "pxefile_addr_r=0x02200000\0" \ |
| 225 | "ramdisk_addr_r=0x02300000\0" \ |
Simon Goldschmidt | 4b2e32e | 2019-03-01 20:12:31 +0100 | [diff] [blame] | 226 | "socfpga_legacy_reset_compat=1\0" \ |
Dalon Westergreen | 451e824 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 227 | BOOTENV |
| 228 | |
| 229 | #endif |
| 230 | #endif |
| 231 | |
Dinh Nguyen | 48275c9 | 2015-12-03 16:05:59 -0600 | [diff] [blame] | 232 | #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ |