blob: fb2dab813794fd5bccfbd4661d87a875258d94ec [file] [log] [blame]
wdenk79fa88f2004-06-07 23:46:25 +00001/*
2 * CODEC
3 */
4
5#include <common.h>
6#include <post.h>
7
8#include "mpc8xx.h"
9
10/***********************************************/
11
12#define MAX_DUSLIC 4
13
14#define NUM_CHANNELS 2
15#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS)
16
17/***********************************************/
18
19#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */
20#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */
21#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */
22#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */
23
24#define COP_READ_CH_0 0xC5
25#define COP_READ_CH_1 0xCD
26#define COP_WRITE_CH_0 0x45
27#define COP_WRITE_CH_1 0x4D
28
29#define POP_READ_CH_0 0xC6
30#define POP_READ_CH_1 0xCE
31#define POP_WRITE_CH_0 0x46
32#define POP_WRITE_CH_1 0x4E
33
34#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */
35#define RST_CMD_DUSLIC_CH_A 0x41
36#define RST_CMD_DUSLIC_CH_B 0x49
37
38#define PCM_RESYNC_CMD_CH_A 0x42
39#define PCM_RESYNC_CMD_CH_B 0x4A
40
41#define ACTIVE_HOOK_LEV_4 0
42#define ACTIVE_HOOK_LEV_12 1
43
44#define SLIC_P_NORMAL 0x01
45
46/************************************************/
47
48#define CODSP_WR 0x00
49#define CODSP_RD 0x80
50#define CODSP_OP 0x40
51#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3)
52#define CODSP_M(x) ((unsigned char)(x) & 7)
53#define CODSP_CMD(x) ((unsigned char)(x) & 7)
54
55/************************************************/
56
57/* command indication ops */
58#define CODSP_M_SLEEP_PWRDN 7
59#define CODSP_M_PWRDN_HIZ 0
60#define CODSP_M_ANY_ACT 2
61#define CODSP_M_RING 5
62#define CODSP_M_ACT_MET 6
63#define CODSP_M_GND_START 4
64#define CODSP_M_RING_PAUSE 1
65
66/* single byte commands */
67#define CODSP_CMD_SOFT_RESET CODSP_CMD(0)
68#define CODSP_CMD_RESET_CH CODSP_CMD(1)
69#define CODSP_CMD_RESYNC CODSP_CMD(2)
70
71/* two byte commands */
72#define CODSP_CMD_SOP CODSP_CMD(4)
73#define CODSP_CMD_COP CODSP_CMD(5)
74#define CODSP_CMD_POP CODSP_CMD(6)
75
76/************************************************/
77
78/* read as 4-bytes */
79#define CODSP_INTREG_INT_CH 0x80000000
80#define CODSP_INTREG_HOOK 0x40000000
81#define CODSP_INTREG_GNDK 0x20000000
82#define CODSP_INTREG_GNDP 0x10000000
83#define CODSP_INTREG_ICON 0x08000000
84#define CODSP_INTREG_VRTLIM 0x04000000
85#define CODSP_INTREG_OTEMP 0x02000000
86#define CODSP_INTREG_SYNC_FAIL 0x01000000
87#define CODSP_INTREG_LM_THRES 0x00800000
88#define CODSP_INTREG_READY 0x00400000
89#define CODSP_INTREG_RSTAT 0x00200000
90#define CODSP_INTREG_LM_OK 0x00100000
91#define CODSP_INTREG_IO4_DU 0x00080000
92#define CODSP_INTREG_IO3_DU 0x00040000
93#define CODSP_INTREG_IO2_DU 0x00020000
94#define CODSP_INTREG_IO1_DU 0x00010000
95#define CODSP_INTREG_DTMF_OK 0x00008000
96#define CODSP_INTREG_DTMF_KEY4 0x00004000
97#define CODSP_INTREG_DTMF_KEY3 0x00002000
98#define CODSP_INTREG_DTMF_KEY2 0x00001000
99#define CODSP_INTREG_DTMF_KEY1 0x00000800
100#define CODSP_INTREG_DTMF_KEY0 0x00000400
101#define CODSP_INTREG_UTDR_OK 0x00000200
102#define CODSP_INTREG_UTDX_OK 0x00000100
103#define CODSP_INTREG_EDSP_FAIL 0x00000080
104#define CODSP_INTREG_CIS_BOF 0x00000008
105#define CODSP_INTREG_CIS_BUF 0x00000004
106#define CODSP_INTREG_CIS_REQ 0x00000002
107#define CODSP_INTREG_CIS_ACT 0x00000001
108
109/************************************************/
110
111/* ======== SOP REG ADDRESSES =======*/
112
113#define REVISION_ADDR 0x00
114#define PCMC1_ADDR 0x05
115#define XCR_ADDR 0x06
116#define INTREG1_ADDR 0x07
117#define INTREG2_ADDR 0x08
118#define INTREG3_ADDR 0x09
119#define INTREG4_ADDR 0x0A
120#define LMRES1_ADDR 0x0D
121#define MASK_ADDR 0x11
122#define IOCTL3_ADDR 0x14
123#define BCR1_ADDR 0x15
124#define BCR2_ADDR 0x16
125#define BCR3_ADDR 0x17
126#define BCR4_ADDR 0x18
127#define BCR5_ADDR 0x19
128#define DSCR_ADDR 0x1A
129#define LMCR1_ADDR 0x1C
130#define LMCR2_ADDR 0x1D
131#define LMCR3_ADDR 0x1E
132#define OFR1_ADDR 0x1F
133#define PCMR1_ADDR 0x21
134#define PCMX1_ADDR 0x25
135#define TSTR3_ADDR 0x2B
136#define TSTR4_ADDR 0x2C
137#define TSTR5_ADDR 0x2D
138
139/* ========= POP REG ADDRESSES ========*/
140
141#define CIS_DAT_ADDR 0x00
142
143#define LEC_LEN_ADDR 0x3A
144#define LEC_POWR_ADDR 0x3B
145#define LEC_DELP_ADDR 0x3C
146#define LEC_DELQ_ADDR 0x3D
147#define LEC_GAIN_XI_ADDR 0x3E
148#define LEC_GAIN_RI_ADDR 0x3F
149#define LEC_GAIN_XO_ADDR 0x40
150#define LEC_RES_1_ADDR 0x41
151#define LEC_RES_2_ADDR 0x42
152
153#define NLP_POW_LPF_ADDR 0x30
154#define NLP_POW_LPS_ADDR 0x31
155#define NLP_BN_LEV_X_ADDR 0x32
156#define NLP_BN_LEV_R_ADDR 0x33
157#define NLP_BN_INC_ADDR 0x34
158#define NLP_BN_DEC_ADDR 0x35
159#define NLP_BN_MAX_ADDR 0x36
160#define NLP_BN_ADJ_ADDR 0x37
161#define NLP_RE_MIN_ERLL_ADDR 0x38
162#define NLP_RE_EST_ERLL_ADDR 0x39
163#define NLP_SD_LEV_X_ADDR 0x3A
164#define NLP_SD_LEV_R_ADDR 0x3B
165#define NLP_SD_LEV_BN_ADDR 0x3C
166#define NLP_SD_LEV_RE_ADDR 0x3D
167#define NLP_SD_OT_DT_ADDR 0x3E
168#define NLP_ERL_LIN_LP_ADDR 0x3F
169#define NLP_ERL_LEC_LP_ADDR 0x40
170#define NLP_CT_LEV_RE_ADDR 0x41
171#define NLP_CTRL_ADDR 0x42
172
173#define UTD_CF_H_ADDR 0x4B
174#define UTD_CF_L_ADDR 0x4C
175#define UTD_BW_H_ADDR 0x4D
176#define UTD_BW_L_ADDR 0x4E
177#define UTD_NLEV_ADDR 0x4F
178#define UTD_SLEV_H_ADDR 0x50
179#define UTD_SLEV_L_ADDR 0x51
180#define UTD_DELT_ADDR 0x52
181#define UTD_RBRK_ADDR 0x53
182#define UTD_RTIME_ADDR 0x54
183#define UTD_EBRK_ADDR 0x55
184#define UTD_ETIME_ADDR 0x56
185
186#define DTMF_LEV_ADDR 0x30
187#define DTMF_TWI_ADDR 0x31
188#define DTMF_NCF_H_ADDR 0x32
189#define DTMF_NCF_L_ADDR 0x33
190#define DTMF_NBW_H_ADDR 0x34
191#define DTMF_NBW_L_ADDR 0x35
192#define DTMF_GAIN_ADDR 0x36
193#define DTMF_RES1_ADDR 0x37
194#define DTMF_RES2_ADDR 0x38
195#define DTMF_RES3_ADDR 0x39
196
197#define CIS_LEV_H_ADDR 0x43
198#define CIS_LEV_L_ADDR 0x44
199#define CIS_BRS_ADDR 0x45
200#define CIS_SEIZ_H_ADDR 0x46
201#define CIS_SEIZ_L_ADDR 0x47
202#define CIS_MARK_H_ADDR 0x48
203#define CIS_MARK_L_ADDR 0x49
204#define CIS_LEC_MODE_ADDR 0x4A
205
206/*=====================================*/
207
208#define HOOK_LEV_ACT_START_ADDR 0x89
209#define RO1_START_ADDR 0x70
210#define RO2_START_ADDR 0x95
211#define RO3_START_ADDR 0x96
212
213#define TG1_FREQ_START_ADDR 0x38
214#define TG1_GAIN_START_ADDR 0x39
215#define TG1_BANDPASS_START_ADDR 0x3B
216#define TG1_BANDPASS_END_ADDR 0x3D
217
218#define TG2_FREQ_START_ADDR 0x40
219#define TG2_GAIN_START_ADDR 0x41
220#define TG2_BANDPASS_START_ADDR 0x43
221#define TG2_BANDPASS_END_ADDR 0x45
222
223/*====================================*/
224
225#define PCM_HW_B 0x80
226#define PCM_HW_A 0x00
227#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */
228#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */
229#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
230
231#define RX_LEV_ADDR 0x28
232#define TX_LEV_ADDR 0x30
233#define Ik1_ADDR 0x83
234
235#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
236#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
237#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
238
239/* Mark the start byte of Duslic parameters that we use with configurator */
240#define Ik1_START_BYTE 3
241#define RX_LEV_START_BYTE 0
242#define TX_LEV_START_BYTE 0
243
244/************************************************/
245
246#define INTREG4_CIS_ACT (1 << 0)
247
248#define BCR1_SLEEP 0x20
249#define BCR1_REVPOL 0x10
250#define BCR1_ACTR 0x08
251#define BCR1_ACTL 0x04
252#define BCR1_SLIC_MASK 0x03
253
254#define BCR2_HARD_POL_REV 0x40
255#define BCR2_TTX 0x20
256#define BCR2_TTX_12K 0x10
257#define BCR2_HIMAN 0x08
258#define BCR2_PDOT 0x01
259
260#define BCR3_PCMX_EN (1 << 4)
261
262#define BCR5_DTMF_EN (1 << 0)
263#define BCR5_DTMF_SRC (1 << 1)
264#define BCR5_LEC_EN (1 << 2)
265#define BCR5_LEC_OUT (1 << 3)
266#define BCR5_CIS_EN (1 << 4)
267#define BCR5_CIS_AUTO (1 << 5)
268#define BCR5_UTDX_EN (1 << 6)
269#define BCR5_UTDR_EN (1 << 7)
270
271#define DSCR_TG1_EN (1 << 0)
272#define DSCR_TG2_EN (1 << 1)
273#define DSCR_PTG (1 << 2)
274#define DSCR_COR8 (1 << 3)
275#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
276
277#define CIS_LEC_MODE_CIS_V23 (1 << 0)
278#define CIS_LEC_MODE_CIS_FRM (1 << 1)
279#define CIS_LEC_MODE_NLP_EN (1 << 2)
280#define CIS_LEC_MODE_UTDR_SUM (1 << 4)
281#define CIS_LEC_MODE_UTDX_SUM (1 << 5)
282#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
283#define CIS_LEC_MODE_LEC_ADAPT (1 << 7)
284
285#define TSTR4_COR_64 (1 << 5)
286
287#define TSTR3_AC_DLB_8K (1 << 2)
288#define TSTR3_AC_DLB_32K (1 << 3)
289#define TSTR3_AC_DLB_4M (1 << 5)
290
291
292#define LMCR1_TEST_EN (1 << 7)
293#define LMCR1_LM_EN (1 << 6)
294#define LMCR1_LM_THM (1 << 5)
295#define LMCR1_LM_ONCE (1 << 2)
296#define LMCR1_LM_MASK (1 << 1)
297
298#define LMCR2_LM_RECT (1 << 5)
299#define LMCR2_LM_SEL_VDD 0x0D
300#define LMCR2_LM_SEL_IO3 0x0A
301#define LMCR2_LM_SEL_IO4 0x0B
302#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F
303
304#define LMCR3_RTR_SEL (1 << 6)
305
306#define LMCR3_RNG_OFFSET_NONE 0x00
307#define LMCR3_RNG_OFFSET_1 0x01
308#define LMCR3_RNG_OFFSET_2 0x02
309#define LMCR3_RNG_OFFSET_3 0x03
310
311#define TSTR5_DC_HOLD (1 << 3)
312
313/************************************************/
314
315#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */
316#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */
317#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
318#define DIVIDER_RATIO_ACCURx100 (22 * 100)
319#define V_AD_x10000 10834L /* VAD = 1.0834 */
320#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
321#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */
322
323#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
324#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
325#define K_INTDC_RECT_OFF 2 /* 2^2 */
326#define RNG_FREQ 25
327#define SAMPLING_FREQ (2000L)
328#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
329#define HOOK_THRESH_RING_START_ADDR 0x8B
330#define RING_PARAMS_START_ADDR 0x70
331
332#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */
333#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */
334#define MAX_V_RING_MEANx100 50
335#define TARGET_V_RING_RMSx100 2720
336#define V_RMS_RING_MAX_DIFFx100 250
337
338#define LM_OK_SRC_IRG_2 (1 << 4)
339
340/************************************************/
341
342#define PORTB (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
343#define PORTC (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
344#define PORTD (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
345
346#define _PORTD_SET(mask, state) \
347 do { \
348 if (state) \
349 PORTD |= mask; \
350 else \
351 PORTD &= ~mask; \
352 } while (0)
353
354#define _PORTB_SET(mask, state) \
355 do { \
356 if (state) \
357 PORTB |= mask; \
358 else \
359 PORTB &= ~mask; \
360 } while (0)
361
362#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
363#define _PORTB_GET(mask) (!!(PORTB & mask))
364
365#define _PORTC_GET(mask) (!!(PORTC & mask))
366
367/* port B */
368#define SPI_RXD (1 << (31 - 28))
369#define SPI_TXD (1 << (31 - 29))
370#define SPI_CLK (1 << (31 - 30))
371
372/* port C */
373#define COM_HOOK1 (1 << (15 - 9))
374#define COM_HOOK2 (1 << (15 - 10))
375
376#ifndef CONFIG_NETTA_SWAPHOOK
377
378#define COM_HOOK3 (1 << (15 - 11))
379#define COM_HOOK4 (1 << (15 - 12))
380
381#else
382
383#define COM_HOOK3 (1 << (15 - 12))
384#define COM_HOOK4 (1 << (15 - 11))
385
386#endif
387
388/* port D */
389#define SPIENC1 (1 << (15 - 9))
390#define SPIENC2 (1 << (15 - 10))
391#define SPIENC3 (1 << (15 - 11))
392#define SPIENC4 (1 << (15 - 14))
393
394#define SPI_DELAY() udelay(1)
395
396static inline unsigned int __SPI_Transfer(unsigned int tx)
397{
398 unsigned int rx;
399 int b;
400
401 rx = 0; b = 8;
402 while (--b >= 0) {
403 _PORTB_SET(SPI_TXD, tx & 0x80);
404 tx <<= 1;
405 _PORTB_TGL(SPI_CLK);
406 SPI_DELAY();
407 rx <<= 1;
408 rx |= _PORTB_GET(SPI_RXD);
409 _PORTB_TGL(SPI_CLK);
410 SPI_DELAY();
411 }
412
413 return rx;
414}
415
416static const char *codsp_dtmf_map = "D1234567890*#ABC";
417
418static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
419static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
420
421static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
422{
423 unsigned int rx;
424 int i;
425
426 /* just some sanity checks */
427 if (cmd == 0 || cmdlen < 0)
428 return -1;
429
430 _PORTD_SET(spienc_mask_tab[duslic_id], 0);
431
432 /* first 2 bytes are without response */
433 i = 2;
434 while (i-- > 0 && cmdlen-- > 0)
435 __SPI_Transfer(*cmd++);
436
437 while (cmdlen-- > 0) {
438 rx = __SPI_Transfer(*cmd++);
439 if (res != 0 && reslen-- > 0)
440 *res++ = (unsigned char)rx;
441 }
442 if (res != 0) {
443 while (reslen-- > 0)
444 *res++ = __SPI_Transfer(0xFF);
445 }
446
447 _PORTD_SET(spienc_mask_tab[duslic_id], 1);
448
449 return 0;
450}
451
452/****************************************************************************/
453
454void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
455{
456 unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
457 codsp_send(duslic_id, &cmd, 1, 0, 0);
458}
459
460void codsp_reset_chip(int duslic_id)
461{
462 static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
463 codsp_send(duslic_id, &cmd, 1, 0, 0);
464}
465
466void codsp_reset_channel(int duslic_id, int channel)
467{
468 unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
469 codsp_send(duslic_id, &cmd, 1, 0, 0);
470}
471
472void codsp_resync_channel(int duslic_id, int channel)
473{
474 unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
475 codsp_send(duslic_id, &cmd, 1, 0, 0);
476}
477
478/****************************************************************************/
479
480void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
481{
482 unsigned char cmd[3];
483
484 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
485 cmd[1] = regno;
486 cmd[2] = val;
487
488 codsp_send(duslic_id, cmd, 3, 0, 0);
489}
490
491void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
492{
493 unsigned char cmd[4];
494
495 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
496 cmd[1] = regno;
497 cmd[2] = (unsigned char)(val >> 8);
498 cmd[3] = (unsigned char)val;
499
500 codsp_send(duslic_id, cmd, 4, 0, 0);
501}
502
503void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
504{
505 unsigned char cmd[5];
506
507 cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
508 cmd[1] = regno;
509 cmd[2] = (unsigned char)(val >> 24);
510 cmd[3] = (unsigned char)(val >> 16);
511 cmd[4] = (unsigned char)(val >> 8);
512 cmd[5] = (unsigned char)val;
513
514 codsp_send(duslic_id, cmd, 6, 0, 0);
515}
516
517unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
518{
519 unsigned char cmd[3];
520 unsigned char res[2];
521
522 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
523 cmd[1] = regno;
524
525 codsp_send(duslic_id, cmd, 2, res, 2);
526
527 return res[1];
528}
529
530unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
531{
532 unsigned char cmd[2];
533 unsigned char res[3];
534
535 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
536 cmd[1] = regno;
537
538 codsp_send(duslic_id, cmd, 2, res, 3);
539
540 return ((unsigned short)res[1] << 8) | res[2];
541}
542
543unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
544{
545 unsigned char cmd[2];
546 unsigned char res[5];
547
548 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
549 cmd[1] = regno;
550
551 codsp_send(duslic_id, cmd, 2, res, 5);
552
553 return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
554}
555
556/****************************************************************************/
557
558void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
559{
560 unsigned char cmd[10];
561
562 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
563 cmd[1] = addr;
564 memcpy(cmd + 2, block, 8);
565 codsp_send(duslic_id, cmd, 10, 0, 0);
566}
567
568void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
569{
570 unsigned char cmd[3];
571
572 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
573 cmd[1] = addr;
574 cmd[2] = val;
575 codsp_send(duslic_id, cmd, 3, 0, 0);
576}
577
578void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
579{
580 unsigned char cmd[3];
581
582 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
583 cmd[1] = addr;
584 cmd[2] = (unsigned char)(val >> 8);
585 cmd[3] = (unsigned char)val;
586
587 codsp_send(duslic_id, cmd, 4, 0, 0);
588}
589
590void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
591{
592 unsigned char cmd[2];
593 unsigned char res[9];
594
595 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
596 cmd[1] = addr;
597 codsp_send(duslic_id, cmd, 2, res, 9);
598 memcpy(block, res + 1, 8);
599}
600
601unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
602{
603 unsigned char cmd[2];
604 unsigned char res[2];
605
606 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
607 cmd[1] = addr;
608 codsp_send(duslic_id, cmd, 2, res, 2);
609 return res[1];
610}
611
612unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
613{
614 unsigned char cmd[2];
615 unsigned char res[3];
616
617 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
618 cmd[1] = addr;
619
620 codsp_send(duslic_id, cmd, 2, res, 3);
621
622 return ((unsigned short)res[1] << 8) | res[2];
623}
624
625/****************************************************************************/
626
627#define MAX_POP_BLOCK 50
628
629void codsp_write_pop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block, int len)
630{
631 unsigned char cmd[2 + MAX_POP_BLOCK];
632
633 if (len > MAX_POP_BLOCK) /* truncate */
634 len = MAX_POP_BLOCK;
635
636 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
637 cmd[1] = addr;
638 memcpy(cmd + 2, block, len);
639 codsp_send(duslic_id, cmd, 2 + len, 0, 0);
640}
641
642void codsp_write_pop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
643{
644 unsigned char cmd[3];
645
646 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
647 cmd[1] = regno;
648 cmd[2] = val;
649
650 codsp_send(duslic_id, cmd, 3, 0, 0);
651}
652
653void codsp_write_pop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
654{
655 unsigned char cmd[4];
656
657 cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
658 cmd[1] = regno;
659 cmd[2] = (unsigned char)(val >> 8);
660 cmd[3] = (unsigned char)val;
661
662 codsp_send(duslic_id, cmd, 4, 0, 0);
663}
664
665void codsp_write_pop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
666{
667 unsigned char cmd[5];
668
669 cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_POP;
670 cmd[1] = regno;
671 cmd[2] = (unsigned char)(val >> 24);
672 cmd[3] = (unsigned char)(val >> 16);
673 cmd[4] = (unsigned char)(val >> 8);
674 cmd[5] = (unsigned char)val;
675
676 codsp_send(duslic_id, cmd, 6, 0, 0);
677}
678
679unsigned char codsp_read_pop_char(int duslic_id, int channel, unsigned char regno)
680{
681 unsigned char cmd[3];
682 unsigned char res[2];
683
684 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
685 cmd[1] = regno;
686
687 codsp_send(duslic_id, cmd, 2, res, 2);
688
689 return res[1];
690}
691
692unsigned short codsp_read_pop_short(int duslic_id, int channel, unsigned char regno)
693{
694 unsigned char cmd[2];
695 unsigned char res[3];
696
697 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
698 cmd[1] = regno;
699
700 codsp_send(duslic_id, cmd, 2, res, 3);
701
702 return ((unsigned short)res[1] << 8) | res[2];
703}
704
705unsigned int codsp_read_pop_int(int duslic_id, int channel, unsigned char regno)
706{
707 unsigned char cmd[2];
708 unsigned char res[5];
709
710 cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
711 cmd[1] = regno;
712
713 codsp_send(duslic_id, cmd, 2, res, 5);
714
715 return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
716}
717
718/****************************************************************************/
719
720struct _coeffs {
721 unsigned char addr;
722 unsigned char values[8];
723};
724
725struct _coeffs ac_coeffs[11] = {
726 { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
727 { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
728 { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
729 { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
730 { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
731 { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
732 { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
733 { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
734 { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
735 { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
736 { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
737};
738
739struct _coeffs ac_coeffs_0dB[11] = {
740 { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
741 { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
742 { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
743 { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
744 { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
745 { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
746 { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
747 { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
748 { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
749 { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
750 { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
751};
752
753struct _coeffs dc_coeffs[9] = {
754 { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
755 { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
756 { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
757 { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
758 { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
759 { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
760 { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
761 { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
762 { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
763};
764
765void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
766{
767 int i;
768
769 for (i = 0; i < tab_size; i++)
770 codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
771}
772
773#define SS_OPEN_CIRCUIT 0
774#define SS_RING_PAUSE 1
775#define SS_ACTIVE 2
776#define SS_ACTIVE_HIGH 3
777#define SS_ACTIVE_RING 4
778#define SS_RINGING 5
779#define SS_ACTIVE_WITH_METERING 6
780#define SS_ONHOOKTRNSM 7
781#define SS_STANDBY 8
782#define SS_MAX 8
783
784static void codsp_set_slic(int duslic_id, int channel, int state)
785{
786 unsigned char v;
787
788 v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
789
790 switch (state) {
791
792 case SS_ACTIVE:
793 codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
794 codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
795 break;
796
797 case SS_ACTIVE_HIGH:
798 codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
799 codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
800 break;
801
802 case SS_ACTIVE_RING:
803 case SS_ONHOOKTRNSM:
804 codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
805 codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
806 break;
807
808 case SS_STANDBY:
809 codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
810 codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
811 break;
812
813 case SS_OPEN_CIRCUIT:
814 codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
815 break;
816
817 case SS_RINGING:
818 codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
819 break;
820
821 case SS_RING_PAUSE:
822 codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
823 break;
824 }
825}
826
827const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
828const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
829
830void retrieve_slic_state(int slic_id)
831{
832 int duslic_id = slic_id >> 1;
833 int channel = slic_id & 1;
834
835 /* Retrieve the state of the SLICs */
836 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
837
838 /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
839 udelay(10000);
840
841 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
842 codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
843 codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
844
845 /* Program Default Hook Ring thresholds */
846 codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
847
848 /* Now program Hook Threshold while Ring and ac RingTrip to max values */
849 codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
850
851 codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
852
853 udelay(40000);
854}
855
856int wait_level_metering_finish(int duslic_id, int channel)
857{
858 int cnt;
859
860 for (cnt = 0; cnt < 1000 &&
861 (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
862
863 return cnt != 1000;
864}
865
866int measure_on_hook_voltages(int slic_id, long *vdd,
867 long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
868{
869 short LM_Result, Offset_Compensation; /* Signed 16 bit */
870 long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
871 unsigned char err_mask = 0;
872 int duslic_id = slic_id >> 1;
873 int channel = slic_id & 1;
874 int i;
875
876 /* measure VDD */
877 /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
878 codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
879
880 /* Activate Test Mode ==> To Enable DC Hold !!! */
881 /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
882 /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
883 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
884
885 udelay(40000);
886
887 /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
888 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
889
890 /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
891 udelay(10000);
892
893 /* Now Read the LM Result Registers */
894 LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
895 VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */
896
897 *vdd = VDD;
898
899 VDD_diff = VDD - TARGET_VDDx100;
900
901 if (VDD_diff < 0)
902 VDD_diff = -VDD_diff;
903
904 if (VDD_diff > VDD_MAX_DIFFx100)
905 err_mask |= 1;
906
907 Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
908
909 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
910 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
911
912 codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
913
914 udelay(40000);
915
916 codsp_write_sop_char(duslic_id, channel,
917 LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
918
919 udelay(40000);
920
921 /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
922 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
923
924 /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
925 udelay(10000);
926
927 /* Now Read the LM Result Registers */
928 LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
929 V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
930
931 V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
932
933 *v_oh_H = V_out;
934
935 Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
936
937 if (Vout_diff < 0)
938 Vout_diff = -Vout_diff;
939
940 if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
941 err_mask |= 2;
942
943 codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
944
945 udelay(40000);
946
947 /* Now Read the LM Result Registers */
948 LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
949
950 V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
951
952 V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
953
954 *v_oh_L = V_out;
955
956 Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
957
958 if (Vout_diff < 0)
959 Vout_diff = -Vout_diff;
960
961 if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
962 err_mask |= 4;
963
964 /* perform ring tests */
965
966 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
967 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
968
969 udelay(40000);
970
971 codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
972
973 /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
974 codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
975
976 /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
977
978 /* Now program Hook Threshold while Ring and ac RingTrip to max values */
979 for(i = 0; i < sizeof(Max_HookRingTh); i++)
980 codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
981
982 codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
983
984 codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
985
986 /* select source for the levelmeter to be IO4-IO3 */
987 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
988
989 udelay(40000);
990
991 /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
992 codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
993
994 udelay(10000);
995
996 /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
997 codsp_write_sop_char(duslic_id, channel,
998 LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
999
1000 udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
1001
1002 if (wait_level_metering_finish(duslic_id, channel)) {
1003
1004 udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
1005
1006 /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
1007 Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1008 Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
1009
1010 /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1011 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
1012
1013 /* Now programm Integrator Offset Registers !!! */
1014 codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
1015
1016 codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
1017
1018 udelay(40000);
1019
1020 /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1021 codsp_write_sop_char(duslic_id, channel,
1022 LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
1023
1024 udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
1025
1026 /* Poll the LM_OK bit to see when Integration Result is Ready */
1027 if (wait_level_metering_finish(duslic_id, channel)) {
1028
1029 udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
1030
1031 /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1032 /* ==>After that Result Regs will be updated every 500us !!!) */
1033 LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1034 V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/
1035
1036 V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
1037
1038 if (V_out < 0)
1039 V_out= -V_out;
1040
1041 if (V_out > MAX_V_RING_MEANx100)
1042 err_mask |= 8;
1043
1044 *ring_mean_v = V_out;
1045 } else {
1046 err_mask |= 8;
1047 *ring_mean_v = 0;
1048 }
1049 } else {
1050 err_mask |= 8;
1051 *ring_mean_v = 0;
1052 }
1053
1054 /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1055 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1056 LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
1057 codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
1058
1059 codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
1060
1061 /* Now Enable Rectifier */
1062 /* select source for the levelmeter to be IO4-IO3 */
1063 codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
1064 LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
1065
1066 /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
1067 codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
1068
1069 udelay(40000);
1070
1071 /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1072 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1073 LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
1074
1075 udelay(40000);
1076
1077 /* Poll the LM_OK bit to see when Integration Result is Ready */
1078 if (wait_level_metering_finish(duslic_id, channel)) {
1079
1080 udelay(10000);
1081
1082 /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1083 /* ==>After that Result Regs will be updated every 500us !!!) */
1084 Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1085 Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
1086
1087 /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1088 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
1089
1090 /* Now programm Integrator Offset Registers !!! */
1091 codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
1092
1093 /* Be sure that a Ring is generated !!!! */
1094 codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
1095
1096 udelay(40000);
1097
1098 /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
1099 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
1100 LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
1101
1102 udelay(40000);
1103
1104 /* Poll the LM_OK bit to see when Integration Result is Ready */
1105 if (wait_level_metering_finish(duslic_id, channel)) {
1106
1107 udelay(10000);
1108
1109 /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
1110 /* ==>After that Result Regs will be updated every 500us !!!) */
1111 LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
1112 V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/
1113
1114 V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */
1115 if (V_out < 0)
1116 V_out = -V_out;
1117
1118 Vout_diff = (V_out - TARGET_V_RING_RMSx100);
1119
1120 if (Vout_diff < 0)
1121 Vout_diff = -Vout_diff;
1122
1123 if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
1124 err_mask |= 16;
1125
1126 *ring_rms_v = V_out;
1127 } else {
1128 err_mask |= 16;
1129 *ring_rms_v = 0;
1130 }
1131 } else {
1132 err_mask |= 16;
1133 *ring_rms_v = 0;
1134 }
1135 /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
1136 codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
1137
1138 retrieve_slic_state(slic_id);
1139
1140 return(err_mask);
1141}
1142
1143int test_dtmf(int slic_id)
1144{
1145 unsigned char code;
1146 unsigned char b;
1147 unsigned int intreg;
1148 int duslic_id = slic_id >> 1;
1149 int channel = slic_id & 1;
1150
1151 for (code = 0; code < 16; code++) {
1152 b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
1153 codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1154 (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
1155 udelay(80000);
1156
1157 intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
1158 if ((intreg & CODSP_INTREG_INT_CH) == 0)
1159 break;
1160
1161 if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
1162 codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
1163 break;
1164
1165 b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
1166 codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1167 b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
1168
1169 udelay(80000);
1170
1171 intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
1172 }
1173
1174 if (code != 16) {
1175 b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
1176 codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
1177 b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
1178 return(1);
1179 }
1180
1181 return(0);
1182}
1183
1184void data_up_persist_time(int duslic_id, int channel, int time_ms)
1185{
1186 unsigned char b;
1187
1188 b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
1189 b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
1190 codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
1191}
1192
1193static void program_dtmf_params(int duslic_id, int channel)
1194{
1195 unsigned char b;
1196
1197 codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
1198 codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
1199 codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
1200 codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
1201 codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
1202 codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
1203 codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
1204 codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
1205 codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
1206 codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
1207
1208 b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
1209 codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
1210}
1211
1212static void codsp_channel_full_reset(int duslic_id, int channel)
1213{
1214
1215 program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
1216 program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
1217
1218 /* program basic configuration registers */
1219 codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
1220 codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
1221 codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
1222 codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
1223 codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
1224
1225 codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */
1226
1227 program_dtmf_params(duslic_id, channel);
1228
1229 codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */
1230
1231 data_up_persist_time(duslic_id, channel, 4);
1232
1233 codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */
1234
1235 codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
1236}
1237
1238static int codsp_chip_full_reset(int duslic_id)
1239{
1240 int i, cnt;
1241 int intreg[NUM_CHANNELS];
1242 unsigned char pcm_resync;
1243 unsigned char revision;
1244
1245 codsp_reset_chip(duslic_id);
1246
1247 udelay(2000);
1248
1249 for (i = 0; i < NUM_CHANNELS; i++)
1250 intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
1251
1252 udelay(1500);
1253
1254 if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
1255 printf("_HOOK(%d) stayed low\n", duslic_id);
1256 return -1;
1257 }
1258
1259 for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
1260 if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
1261 pcm_resync |= 1 << i;
1262 }
1263
1264 for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
1265 for (i = 0; i < NUM_CHANNELS; i++)
1266 codsp_resync_channel(duslic_id, i);
1267
1268 udelay(2000);
1269
1270 pcm_resync = 0;
1271
1272 for (i = 0; i < NUM_CHANNELS; i++) {
1273 if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
1274 pcm_resync |= 1 << i;
1275 }
1276 }
1277
1278 if (cnt == 5) {
1279 printf("PCM_Resync(%u) not completed\n", duslic_id);
1280 return -2;
1281 }
1282
1283 revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
1284 printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
1285
1286 codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */
1287
1288 for (i = 0; i < NUM_CHANNELS; i++) {
1289 codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
1290 codsp_channel_full_reset(duslic_id, i);
1291 }
1292
1293 return 0;
1294}
1295
1296int slic_self_test(int duslic_mask)
1297{
1298 int slic;
1299 int i;
1300 int r;
1301 long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
1302 const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
1303 int error = 0;
1304
1305 for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
1306 if (duslic_mask & (1 << (slic >> 1))) {
1307 r = measure_on_hook_voltages(slic, &vdd,
1308 &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
1309
1310 printf("SLIC %u measured voltages (x100):\n\t"
1311 "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
1312 slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
1313
1314 if (r != 0)
1315 error |= 1 << slic;
1316
1317 for (i = 0; i < 5; i++)
1318 if (r & (1 << i))
1319 printf("\t%s out of range\n", err_txt[i]);
1320 }
1321 }
1322
1323 for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
1324 if (duslic_mask & (1 << (slic >> 1))) {
1325 printf("SLIC %u VOICE PATH...CHECKING", slic);
1326 printf("\rSLIC %u VOICE PATH...%s\n", slic,
1327 (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED ");
1328
1329 if (r != 0)
1330 error |= 1 << slic;
1331 }
1332 }
1333
1334 return(error);
1335}
1336
1337#if defined(CONFIG_NETTA_ISDN)
1338
1339#define SPIENS1 (1 << (31 - 15))
1340#define SPIENS2 (1 << (31 - 19))
1341
1342static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
1343int s_initialized = 0;
1344
1345static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
1346{
1347 unsigned int rx, v;
1348
1349 _PORTB_SET(spiens_mask_tab[s_id], 0);
1350
1351 rx = __SPI_Transfer(address);
1352
1353 switch (address & 0xF0) {
1354 case 0x60: /* write byte register */
1355 case 0x70:
1356 rx = __SPI_Transfer(value);
1357 break;
1358
1359 case 0xE0: /* read R6 register */
1360 v = __SPI_Transfer(0);
1361
1362 rx = (rx << 8) | v;
1363
1364 break;
1365
1366 case 0xF0: /* read byte register */
1367 rx = __SPI_Transfer(0);
1368
1369 break;
1370 }
1371
1372 _PORTB_SET(spiens_mask_tab[s_id], 1);
1373
1374 return rx;
1375}
1376
1377static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
1378{
1379 unsigned int address;
1380 unsigned int v;
1381
1382 address = 0x70 | (regno & 15);
1383 val &= 0xff;
1384
1385 v = s_transfer_internal(s_id, address, val);
1386}
1387
1388static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
1389{
1390 unsigned int address;
1391 unsigned int v;
1392
1393 address = 0x70 | (regno & 15);
1394 val &= 0xff;
1395
1396 v = s_transfer_internal(s_id, address, val);
1397}
1398
1399static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
1400{
1401 unsigned int address;
1402 unsigned int v;
1403
1404 address = (regno & 7) << 4;
1405 val &= 0xf;
1406
1407 v = s_transfer_internal(s_id, address | val, 0x00);
1408}
1409
1410#define BR7_IFR 0x08 /* IDL2 free run */
1411#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */
1412
1413#define BR15_OVRL_REG_EN 0x80
1414#define OR7_D3VR 0x80 /* disable 3V regulator */
1415
1416#define OR8_TEME 0x10 /* TE mode enable */
1417#define OR8_MME 0x08 /* master mode enable */
1418
1419void s_initialize(void)
1420{
1421 int s_id;
1422
1423 for (s_id = 0; s_id < 2; s_id++) {
1424 s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
1425 s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
1426 s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
1427 s_write_OR(s_id, 7, OR7_D3VR);
1428 s_write_OR(s_id, 6, 0);
1429 s_write_BR(s_id, 15, 0);
1430 s_write_NR(s_id, 3, 0);
1431 }
1432}
1433
1434#endif
1435
1436int board_post_codec(int flags)
1437{
1438 int j;
1439 int r;
1440 int duslic_mask;
1441
1442 printf("board_post_dsp\n");
1443
1444#if defined(CONFIG_NETTA_ISDN)
1445 if (s_initialized == 0) {
1446 s_initialize();
1447 s_initialized = 1;
1448
1449 printf("s_initialized\n");
1450
1451 udelay(20000);
1452 }
1453#endif
1454 duslic_mask = 0;
1455
1456 for (j = 0; j < MAX_DUSLIC; j++) {
1457 if (codsp_chip_full_reset(j) < 0)
1458 printf("Error initializing DuSLIC#%d\n", j);
1459 else
1460 duslic_mask |= 1 << j;
1461 }
1462
1463 if (duslic_mask != 0) {
1464 printf("Testing SLICs...\n");
1465
1466 r = slic_self_test(duslic_mask);
1467 for (j = 0; j < MAX_SLICS; j++) {
1468 if (duslic_mask & (1 << (j >> 1)))
1469 printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
1470 }
1471 }
1472 printf("DuSLIC self test finished\n");
1473
1474 return 0; /* return -1 on error */
1475}